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Advanced Parallel Processing Technologies 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009 Proceedings /
This book constitutes the refereed proceedings of the 8th International Workshop on Advanced Parallel Processing Technologies, APPT 2009, held in Rapperswil, Switzerland, in August 2009. The 36 revised full papers presented were carefully reviewed and selected from 76 submissions. All current aspect...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Berlin, Heidelberg :
Springer Berlin Heidelberg : Imprint: Springer,
2009.
|
| Edición: | 1st ed. 2009. |
| Colección: | Theoretical Computer Science and General Issues,
5737 |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 245 | 1 | 0 | |a Advanced Parallel Processing Technologies |h [electronic resource] : |b 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009 Proceedings / |c edited by Yong Dou, Ralf Gruber, Josef Joller. |
| 250 | |a 1st ed. 2009. | ||
| 264 | 1 | |a Berlin, Heidelberg : |b Springer Berlin Heidelberg : |b Imprint: Springer, |c 2009. | |
| 300 | |a XII, 478 p. |b online resource. | ||
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| 490 | 1 | |a Theoretical Computer Science and General Issues, |x 2512-2029 ; |v 5737 | |
| 505 | 0 | |a Architecture -- A Fast Scheme to Investigate Thermal-Aware Scheduling Policy for Multicore Processors -- Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs -- An Efficient Lightweight Shared Cache Design for Chip Multiprocessors -- A Novel Cache Organization for Tiled Chip Multiprocessor -- A Performance Model for Run-Time Reconfigurable Hardware Accelerator -- SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework -- Implementation of Rotation Invariant Multi-View Face Detection on FPGA -- The Design and Evaluation of a Selective Way Based Trace Cache -- A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA -- L1 Collective Cache: Managing Shared Data for Chip Multiprocessors -- Graphical Processing Unit -- Efficient Multiplication of Polynomials on Graphics Hardware -- Performance Optimization Strategies of High Performance Computing on GPU -- A Practical Approach of Curved Ray Prestack Kirchhoff Time Migration on GPGPU -- GCSim: A GPU-Based Trace-Driven Simulator for Multi-level Cache -- A Hybrid Parallel Signature Matching Model for Network Security Applications Using SIMD GPU -- Grid -- HPVZ: A High Performance Virtual Computing Environment for Super Computers -- High Performance Support of Lustre over Customized HSNI for HPC -- ViroLab Security and Virtual Organization Infrastructure -- E2EDSM: An Edge-to-Edge Data Service Model for Mass Streaming Media Transmission -- Grid Scheduling -- Iso-Level CAFT: How to Tackle the Combination of Communication Overhead Reduction and Fault Tolerance Scheduling -- MaGate Simulator: A Simulation Environment for a Decentralized Grid Scheduler -- Mobile Applications -- A Distributed Shared Memory Architecture for Occasionally Connected Mobile Environments -- Time-Adaptive Vertical Handoff Triggering Methods for Heterogeneous Systems -- Energy-Saving Topology Control for Heterogeneous Ad Hoc Networks -- Parallel Applications -- Computational Performance of a Parallelized Three-Dimensional High-Order Spectral Element Toolbox -- Research on Evaluation of Parallelization on an Embedded Multicore Platform -- MapReduce-Based Pattern Finding Algorithm Applied in Motif Detection for Prescription Compatibility Network -- Parallelization of the LEMan Code with MPI and OpenMP -- The Recursive Dual-Net and Its Applications -- Parallelization Strategies for Mixed Regular-Irregular Applications on Multicore-Systems -- Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices -- Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture -- Implementing Fast Packet Filters by Software Pipelining on x86 Processors -- Parallel Libraries -- OSL: Optimized Bulk Synchronous Parallel Skeletons on Distributed Arrays -- Performance -- Evaluating SPLASH-2 Applications Using MapReduce -- MPTD: A Scalable and Flexible Performance Prediction Framework for Parallel Systems. | |
| 520 | |a This book constitutes the refereed proceedings of the 8th International Workshop on Advanced Parallel Processing Technologies, APPT 2009, held in Rapperswil, Switzerland, in August 2009. The 36 revised full papers presented were carefully reviewed and selected from 76 submissions. All current aspects in parallel and distributed computing are addressed ranging from hardware and software issues to algorithmic aspects and advanced applications. The papers are organized in topical sections on architecture, graphical processing unit, grid, grid scheduling, mobile application, parallel application, parallel libraries and performance. | ||
| 650 | 0 | |a Computer science. | |
| 650 | 1 | 4 | |a Theory of Computation. |
| 650 | 2 | 4 | |a Computer Science. |
| 700 | 1 | |a Dou, Yong. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Gruber, Ralf. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Joller, Josef. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
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| 776 | 0 | 8 | |i Printed edition: |z 9783642036453 |
| 776 | 0 | 8 | |i Printed edition: |z 9783642036439 |
| 830 | 0 | |a Theoretical Computer Science and General Issues, |x 2512-2029 ; |v 5737 | |
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