Transactions on High-Performance Embedded Architectures and Compilers II

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Stenström, Per (Editor ), Whalley, David (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2009.
Edición:1st ed. 2009.
Colección:Transactions on High-Performance Embedded Architectures and Compilers, 5470
Temas:
Computer programming.
Computer networks .
Computer systems.
Computer arithmetic and logic units.
Microprocessors.
Computer architecture.
Computer input-output equipment.
Programming Techniques.
Computer Communication Networks.
Computer System Implementation.
Arithmetic and Logic Structures.
Processor Architectures.
Input/Output and Data Communications.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Special Section on High-Performance Embedded Architectures and Compilers
  • Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches
  • Compiler-Assisted Memory Encryption for Embedded Processors
  • Branch Predictor Warmup for Sampled Simulation through Branch History Matching
  • Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems
  • Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization
  • Regular Papers
  • Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors
  • Fetch Gating Control through Speculative Instruction Window Weighting
  • Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers
  • Linux Kernel Compaction through Cold Code Swapping
  • Complexity Effective Bypass Networks
  • A Context-Parameterized Model for Static Analysis of Execution Times
  • Reexecution and Selective Reuse in Checkpoint Processors
  • Compiler Support for Code Size Reduction Using a Queue-Based Processor
  • Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC
  • Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.

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