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High Performance Embedded Architectures and Compilers Fourth International Conference, HiPEAC 2009 /
This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | , , , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Berlin, Heidelberg :
Springer Berlin Heidelberg : Imprint: Springer,
2009.
|
| Edición: | 1st ed. 2009. |
| Colección: | Theoretical Computer Science and General Issues,
5409 |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 245 | 1 | 0 | |a High Performance Embedded Architectures and Compilers |h [electronic resource] : |b Fourth International Conference, HiPEAC 2009 / |c edited by André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer. |
| 250 | |a 1st ed. 2009. | ||
| 264 | 1 | |a Berlin, Heidelberg : |b Springer Berlin Heidelberg : |b Imprint: Springer, |c 2009. | |
| 300 | |a XIII, 420 p. |b online resource. | ||
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| 490 | 1 | |a Theoretical Computer Science and General Issues, |x 2512-2029 ; |v 5409 | |
| 505 | 0 | |a Invited Program -- Keynote: Challenges on the Road to Exascale Computing -- Keynote: Compilers in the Manycore Era -- I Dynamic Translation and Optimisation -- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering -- Predictive Runtime Code Scheduling for Heterogeneous Architectures -- Collective Optimization -- High Speed CPU Simulation Using LTU Dynamic Binary Translation -- II Low Level Scheduling -- Integrated Modulo Scheduling for Clustered VLIW Architectures -- Software Pipelining in Nested Loops with Prolog-Epilog Merging -- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables -- III Parallelism and Resource Control -- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor -- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor -- A Hardware Task Scheduler for Embedded Video Processing -- Finding Stress Patterns in Microprocessor Workloads -- IV Communication -- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications -- MPSoC Design Using Application-Specific Architecturally Visible Communication -- Communication Based Proactive Link Power Management -- V Mapping for CMPs -- Mapping and Synchronizing Streaming Applications on Cell Processors -- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors -- Accomodating Diversity in CMPs with Heterogeneous Frequencies -- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip -- VI Power -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines -- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic -- Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures -- VII Cache Issues -- Revisiting Cache Block Superloading -- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors -- In-Network Caching for Chip Multiprocessors -- VIII Parallel Embedded Applications -- Parallel LDPC Decoding on the Cell/B.E. Processor -- Parallel H.264 Decoding on an Embedded Multicore Processor. | |
| 520 | |a This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications. | ||
| 650 | 0 | |a Computer systems. | |
| 650 | 0 | |a Computer arithmetic and logic units. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 0 | |a Computer input-output equipment. | |
| 650 | 0 | |a Logic design. | |
| 650 | 0 | |a Computer networks . | |
| 650 | 1 | 4 | |a Computer System Implementation. |
| 650 | 2 | 4 | |a Arithmetic and Logic Structures. |
| 650 | 2 | 4 | |a Processor Architectures. |
| 650 | 2 | 4 | |a Input/Output and Data Communications. |
| 650 | 2 | 4 | |a Logic Design. |
| 650 | 2 | 4 | |a Computer Communication Networks. |
| 700 | 1 | |a Seznec, André. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Emer, Joel. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a O'Boyle, Michael. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Martonosi, Margaret. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Ungerer, Theo. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9783540929918 |
| 776 | 0 | 8 | |i Printed edition: |z 9783540929895 |
| 830 | 0 | |a Theoretical Computer Science and General Issues, |x 2512-2029 ; |v 5409 | |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-3-540-92990-1 |z Texto Completo |
| 912 | |a ZDB-2-SCS | ||
| 912 | |a ZDB-2-SXCS | ||
| 912 | |a ZDB-2-LNC | ||
| 950 | |a Computer Science (SpringerNature-11645) | ||
| 950 | |a Computer Science (R0) (SpringerNature-43710) | ||