|
|
|
|
| LEADER |
00000nam a22000005i 4500 |
| 001 |
978-3-540-78610-8 |
| 003 |
DE-He213 |
| 005 |
20230224003151.0 |
| 007 |
cr nn 008mamaa |
| 008 |
100301s2008 gw | s |||| 0|eng d |
| 020 |
|
|
|a 9783540786108
|9 978-3-540-78610-8
|
| 024 |
7 |
|
|a 10.1007/978-3-540-78610-8
|2 doi
|
| 050 |
|
4 |
|a QA75.5-76.95
|
| 072 |
|
7 |
|a UYA
|2 bicssc
|
| 072 |
|
7 |
|a COM014000
|2 bisacsh
|
| 072 |
|
7 |
|a UYA
|2 thema
|
| 082 |
0 |
4 |
|a 004.0151
|2 23
|
| 245 |
1 |
0 |
|a Reconfigurable Computing: Architectures, Tools, and Applications
|h [electronic resource] :
|b 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings /
|c edited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz.
|
| 250 |
|
|
|a 1st ed. 2008.
|
| 264 |
|
1 |
|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2008.
|
| 300 |
|
|
|a XIV, 346 p.
|b online resource.
|
| 336 |
|
|
|a text
|b txt
|2 rdacontent
|
| 337 |
|
|
|a computer
|b c
|2 rdamedia
|
| 338 |
|
|
|a online resource
|b cr
|2 rdacarrier
|
| 347 |
|
|
|a text file
|b PDF
|2 rda
|
| 490 |
1 |
|
|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 4943
|
| 505 |
0 |
|
|a Keynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing -- The von Neumann Syndrome and the CS Education Dilemma -- Programming and Compilation -- Optimal Unroll Factor for Reconfigurable Architectures -- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems -- DNA and String Processing Applications -- DNA Physical Mapping on a Reconfigurable Platform -- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs -- Scientific Applications -- A Custom Processor for a TDMA Solver in a CFD Application -- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation -- Reconfigurable Computing Hardware and Systems -- Physical Design of FPGA Interconnect to Prevent Information Leakage -- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs -- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems -- Image Processing -- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor -- A Parallel Hardware Architecture for Image Feature Detection -- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System -- Run-Time Behavior -- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems -- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors with Hybrid Accelerators -- The Instruction-Set Extension Problem: A Survey -- Random Number Generation and Financial Computation -- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator -- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA -- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models -- Posters -- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor -- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard -- Creating the World's Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications -- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs -- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures -- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications -- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip -- Efficiency of Dynamic Reconfigurable Datapath Extensions - A Case Study -- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices -- Data Reallocation by Exploiting FPGA Configuration Mechanisms -- A Networked, Lightweight and Partially Reconfigurable Platform -- Neuromolecularware - A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis -- An FPGA Configuration Scheme for Bitstream Protection -- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture.
|
| 650 |
|
0 |
|a Computer science.
|
| 650 |
|
0 |
|a Computers.
|
| 650 |
|
0 |
|a Microprocessors.
|
| 650 |
|
0 |
|a Computer architecture.
|
| 650 |
|
0 |
|a Computer networks .
|
| 650 |
|
0 |
|a Electronic digital computers-Evaluation.
|
| 650 |
|
0 |
|a Computer systems.
|
| 650 |
1 |
4 |
|a Theory of Computation.
|
| 650 |
2 |
4 |
|a Computer Hardware.
|
| 650 |
2 |
4 |
|a Processor Architectures.
|
| 650 |
2 |
4 |
|a Computer Communication Networks.
|
| 650 |
2 |
4 |
|a System Performance and Evaluation.
|
| 650 |
2 |
4 |
|a Computer System Implementation.
|
| 700 |
1 |
|
|a Woods, Roger.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Compton, Katherine.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Bourganis, Christos.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Diniz, Pedro C.
|e editor.
|0 (orcid)0000-0003-3131-9367
|1 https://orcid.org/0000-0003-3131-9367
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 710 |
2 |
|
|a SpringerLink (Online service)
|
| 773 |
0 |
|
|t Springer Nature eBook
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9783540871101
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9783540786092
|
| 830 |
|
0 |
|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 4943
|
| 856 |
4 |
0 |
|u https://doi.uam.elogim.com/10.1007/978-3-540-78610-8
|z Texto Completo
|
| 912 |
|
|
|a ZDB-2-SCS
|
| 912 |
|
|
|a ZDB-2-SXCS
|
| 912 |
|
|
|a ZDB-2-LNC
|
| 950 |
|
|
|a Computer Science (SpringerNature-11645)
|
| 950 |
|
|
|a Computer Science (R0) (SpringerNature-43710)
|
