|
|
|
|
| LEADER |
00000nam a22000005i 4500 |
| 001 |
978-3-540-77560-7 |
| 003 |
DE-He213 |
| 005 |
20230406051836.0 |
| 007 |
cr nn 008mamaa |
| 008 |
100301s2008 gw | s |||| 0|eng d |
| 020 |
|
|
|a 9783540775607
|9 978-3-540-77560-7
|
| 024 |
7 |
|
|a 10.1007/978-3-540-77560-7
|2 doi
|
| 050 |
|
4 |
|a QA76.9.C62
|
| 072 |
|
7 |
|a UK
|2 bicssc
|
| 072 |
|
7 |
|a COM036000
|2 bisacsh
|
| 072 |
|
7 |
|a UK
|2 thema
|
| 082 |
0 |
4 |
|a 004.01513
|2 23
|
| 245 |
1 |
0 |
|a High Performance Embedded Architectures and Compilers
|h [electronic resource] :
|b Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /
|c edited by Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer.
|
| 250 |
|
|
|a 1st ed. 2008.
|
| 264 |
|
1 |
|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2008.
|
| 300 |
|
|
|a XIII, 400 p.
|b online resource.
|
| 336 |
|
|
|a text
|b txt
|2 rdacontent
|
| 337 |
|
|
|a computer
|b c
|2 rdamedia
|
| 338 |
|
|
|a online resource
|b cr
|2 rdacarrier
|
| 347 |
|
|
|a text file
|b PDF
|2 rda
|
| 490 |
1 |
|
|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 4917
|
| 505 |
0 |
|
|a Invited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.
|
| 650 |
|
0 |
|a Computer arithmetic and logic units.
|
| 650 |
|
0 |
|a Compilers (Computer programs).
|
| 650 |
|
0 |
|a Computer systems.
|
| 650 |
|
0 |
|a Microprocessors.
|
| 650 |
|
0 |
|a Computer architecture.
|
| 650 |
|
0 |
|a Computer input-output equipment.
|
| 650 |
|
0 |
|a Logic design.
|
| 650 |
1 |
4 |
|a Arithmetic and Logic Structures.
|
| 650 |
2 |
4 |
|a Compilers and Interpreters.
|
| 650 |
2 |
4 |
|a Computer System Implementation.
|
| 650 |
2 |
4 |
|a Processor Architectures.
|
| 650 |
2 |
4 |
|a Input/Output and Data Communications.
|
| 650 |
2 |
4 |
|a Logic Design.
|
| 700 |
1 |
|
|a Stenström, Per.
|e editor.
|0 (orcid)0000-0002-7441-8245
|1 https://orcid.org/0000-0002-7441-8245
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Dubois, Michel.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Katevenis, Manolis.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Gupta, Rajiv.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Ungerer, Theo.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 710 |
2 |
|
|a SpringerLink (Online service)
|
| 773 |
0 |
|
|t Springer Nature eBook
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9783540847083
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9783540775591
|
| 830 |
|
0 |
|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 4917
|
| 856 |
4 |
0 |
|u https://doi.uam.elogim.com/10.1007/978-3-540-77560-7
|z Texto Completo
|
| 912 |
|
|
|a ZDB-2-SCS
|
| 912 |
|
|
|a ZDB-2-SXCS
|
| 912 |
|
|
|a ZDB-2-LNC
|
| 950 |
|
|
|a Computer Science (SpringerNature-11645)
|
| 950 |
|
|
|a Computer Science (R0) (SpringerNature-43710)
|
