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|a 9783540766506
|9 978-3-540-76650-6
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|a 10.1007/978-3-540-76650-6
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|a Formal Methods and Software Engineering
|h [electronic resource] :
|b 9th International Conference on Formal Engineering Methods, ICFEM 2007, Boca Raton, Florida, USA, November 14-15, 2007, Proceedings /
|c edited by Michael Butler, Michael G. Hinchey, Maria M. Larrondo-Petrie.
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| 250 |
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|a 1st ed. 2007.
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|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2007.
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|a VIII, 387 p.
|b online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
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|a online resource
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|a text file
|b PDF
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|a Programming and Software Engineering,
|x 2945-9168 ;
|v 4789
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| 505 |
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|a Invited Talks -- A System Development Process with Event-B and the Rodin Platform -- Challenges in Software Certification -- Security and Knowledge -- Integrating Formal Methods with System Management -- Formal Engineering of XACML Access Control Policies in VDM++ -- A Verification Framework for Agent Knowledge -- Embedded Systems -- From Model-Based Design to Formal Verification of Adaptive Embedded Systems -- Machine-Assisted Proof Support for Validation Beyond Simulink -- VeSTA: A Tool to Verify the Correct Integration of a Component in a Composite Timed System -- Testing -- Integrating Specification-Based Review and Testing for Detecting Errors in Programs -- Testing for Refinement in CSP -- Reducing Test Sequence Length Using Invertible Sequences -- Automated Analysis -- Model Checking with SAT-Based Characterization of ACTL Formulas -- Automating Refinement Checking in Probabilistic System Design -- Model Checking in Practice: Analysis of Generic Bootloader Using SPIN -- Model Checking Propositional Projection Temporal Logic Based on SPIN -- Hardware -- A Denotational Semantics for Handel-C Hardware Compilation -- Automatic Generation of Verified Concurrent Hardware -- Modeling and Verification of Master/Slave Clock Synchronization Using Hybrid Automata and Model-Checking -- Concurrency -- Efficient Symbolic Execution of Large Quantifications in a Process Algebra -- Formalizing SANE Virtual Processor in Thread Algebra -- Calculating and Composing Progress Properties in Terms of the Leads-to Relation -- Erratum -- Erratum to: Challenges in Software Certification.
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|a Software engineering.
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| 650 |
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|a Computer programming.
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|a Computer science.
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| 650 |
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|a Compilers (Computer programs).
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| 650 |
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|a Software Engineering.
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| 650 |
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|a Programming Techniques.
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| 650 |
2 |
4 |
|a Models of Computation.
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| 650 |
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|a Computer Science Logic and Foundations of Programming.
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| 650 |
2 |
4 |
|a Compilers and Interpreters.
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| 700 |
1 |
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|a Butler, Michael.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
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|a Hinchey, Michael G.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
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|a Larrondo-Petrie, Maria M.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 710 |
2 |
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|a SpringerLink (Online service)
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| 773 |
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|t Springer Nature eBook
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| 776 |
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|i Printed edition:
|z 9783540845782
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| 776 |
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|i Printed edition:
|z 9783540766483
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| 830 |
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|a Programming and Software Engineering,
|x 2945-9168 ;
|v 4789
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| 856 |
4 |
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|u https://doi.uam.elogim.com/10.1007/978-3-540-76650-6
|z Texto Completo
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| 950 |
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|a Computer Science (SpringerNature-11645)
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| 950 |
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|a Computer Science (R0) (SpringerNature-43710)
|
