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Evolvable Systems: From Biology to Hardware 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings /

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Zeng, Sanyou (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2007.
Edición:1st ed. 2007.
Colección:Theoretical Computer Science and General Issues, 4684
Temas:
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Digital Hardware Evolution
  • An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification
  • Design of Electronic Circuits Using a Divide-and-Conquer Approach
  • Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel
  • An Intrinsic Evolvable Hardware Based on Multiplexer Module Array
  • Estimating Array Connectivity and Applying Multi-output Node Structure in Evolutionary Design of Digital Circuits
  • Research on the Online Evaluation Approach for the Digital Evolvable Hardware
  • Research on Multi-objective On-Line Evolution Technology of Digital Circuit Based on FPGA Model
  • Evolutionary Design of Generic Combinational Multipliers Using Development
  • Analog Hardware Evolution
  • Automatic Synthesis of Practical Passive Filters Using Clonal Selection Principle-Based Gene Expression Programming
  • Research on Fault-Tolerance of Analog Circuits Based on Evolvable Hardware
  • Analog Circuit Evolution Based on FPTA-2
  • Bio-inspired Systems
  • Knowledge Network Management System with Medicine Self Repairing Strategy
  • Design of a Cell in Embryonic Systems with Improved Efficiency and Fault-Tolerance
  • Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit
  • Bio-inspired Systems with Self-developing Mechanisms
  • Development of a Tiny Computer-Assisted Wireless EEG Biofeedback System
  • Steps Forward to Evolve Bio-inspired Embryonic Cell-Based Electronic Systems
  • Evolution of Polymorphic Self-checking Circuits
  • Mechanical Hardware Evolution
  • Sliding Algorithm for Reconfigurable Arrays of Processors
  • System-Level Modeling and Multi-objective Evolutionary Design of Pipelined FFT Processors for Wireless OFDM Receivers
  • Reducing the Area on a Chip Using a Bank of Evolved Filters
  • Evolutionary Design
  • Walsh Function Systems: The Bisectional Evolutional Generation Pattern
  • Extrinsic Evolvable Hardware on the RISA Architecture
  • Evolving and Analysing "Useful" Redundant Logic
  • Adaptive Transmission Technique in Underwater Acoustic Wireless Communication
  • Autonomous Robot Path Planning Based on Swarm Intelligence and Stream Functions
  • Research on Adaptive System of the BTT-45 Air-to-Air Missile Based on Multilevel Hierarchical Intelligent Controller
  • The Design of an Evolvable On-Board Computer
  • Evolutionary Algorithms in Hardware Design
  • Extending Artificial Development: Exploiting Environmental Information for the Achievement of Phenotypic Plasticity
  • UDT-Based Multi-objective Evolutionary Design of Passive Power Filters of a Hybrid Power Filter System
  • Designing Electronic Circuits by Means of Gene Expression Programming II
  • Designing Polymorphic Circuits with Evolutionary Algorithm Based on Weighted Sum Method
  • Robust and Efficient Multi-objective Automatic Adjustment for Optical Axes in Laser Systems Using Stochastic Binary Search Algorithm
  • Minimization of the Redundant Sensor Nodes in Dense Wireless Sensor Networks
  • Evolving in Extended Hamming Distance Space: Hierarchical Mutation Strategy and Local Learning Principle for EHW
  • Hardware Implementation of Evolutionary Algorithms
  • Adaptive and Evolvable Analog Electronics for Space Applications
  • Improving Flexibility in On-Line Evolvable Systems by Reconfigurable Computing
  • Evolutionary Design of Resilient Substitution Boxes: From Coding to Hardware Implementation
  • A Sophisticated Architecture for Evolutionary Multiobjective Optimization Utilizing High Performance DSP
  • FPGA-Based Genetic Algorithm Kernel Design
  • Using Systolic Technique to Accelerate an EHW Engine for Lossless Image Compression.