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978-3-540-71528-3 |
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|a 9783540715283
|9 978-3-540-71528-3
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|a 10.1007/978-3-540-71528-3
|2 doi
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|a 004.0151
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|a Transactions on High-Performance Embedded Architectures and Compilers I
|h [electronic resource] /
|c edited by Mike O'Boyle, Francois Bodin, Marcelo Cintra, Sally A. McKee.
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| 250 |
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|a 1st ed. 2007.
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| 264 |
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1 |
|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2007.
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| 300 |
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|a XVI, 368 p.
|b online resource.
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| 336 |
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
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|a text file
|b PDF
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|a Transactions on High-Performance Embedded Architectures and Compilers,
|x 1864-3078 ;
|v 4050
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| 505 |
0 |
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|a High Performance Processor Chips -- High Performance Processor Chips -- High-Performance Embedded Architecture and Compilation Roadmap -- 1: First International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005. Best Papers -- to Part 1 -- Quick and Practical Run-Time Evaluation of Multiple Program Optimizations -- Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems -- GCH: Hints for Triggering Garbage Collections -- Memory-Centric Security Architecture -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- 2: Optimizing Compilers -- to Part 2 -- Convergent Compilation Applied to Loop Unrolling -- Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations -- Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures -- Automatic Discovery of Coarse-Grained Parallelism in Media Applications -- An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors -- 3: ACM International Conference on Computing Frontiers 2006. Best Papers -- to Part 3 -- Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology -- Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture -- Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors -- Selective Code Compression Scheme for Embedded Systems -- A Prefetching Algorithm for Multi-speed Disks -- Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation.
|
| 650 |
|
0 |
|a Computer science.
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| 650 |
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|a Computer arithmetic and logic units.
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| 650 |
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|a Microprocessors.
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| 650 |
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|a Computer architecture.
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| 650 |
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|a Computer input-output equipment.
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| 650 |
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|a Logic design.
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| 650 |
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|a Computer networks .
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| 650 |
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4 |
|a Theory of Computation.
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| 650 |
2 |
4 |
|a Arithmetic and Logic Structures.
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| 650 |
2 |
4 |
|a Processor Architectures.
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| 650 |
2 |
4 |
|a Input/Output and Data Communications.
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| 650 |
2 |
4 |
|a Logic Design.
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| 650 |
2 |
4 |
|a Computer Communication Networks.
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| 700 |
1 |
|
|a O'Boyle, Mike.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
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|a Bodin, Francois.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
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|a Cintra, Marcelo.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
|
|a McKee, Sally A.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 710 |
2 |
|
|a SpringerLink (Online service)
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| 773 |
0 |
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|t Springer Nature eBook
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9783540836759
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| 776 |
0 |
8 |
|i Printed edition:
|z 9783540715276
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| 830 |
|
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|a Transactions on High-Performance Embedded Architectures and Compilers,
|x 1864-3078 ;
|v 4050
|
| 856 |
4 |
0 |
|u https://doi.uam.elogim.com/10.1007/978-3-540-71528-3
|z Texto Completo
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| 912 |
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|a ZDB-2-SCS
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| 912 |
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|a ZDB-2-SXCS
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| 912 |
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|a ZDB-2-LNC
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| 950 |
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|a Computer Science (SpringerNature-11645)
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| 950 |
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|a Computer Science (R0) (SpringerNature-43710)
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