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978-3-540-69338-3 |
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DE-He213 |
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20230406040521.0 |
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100301s2007 gw | s |||| 0|eng d |
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|a 9783540693383
|9 978-3-540-69338-3
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|a 10.1007/978-3-540-69338-3
|2 doi
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|a 004.0151
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|a High Performance Embedded Architectures and Compilers
|h [electronic resource] :
|b Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings /
|c edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer.
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| 250 |
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|a 1st ed. 2007.
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| 264 |
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|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2007.
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| 300 |
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|a XI, 307 p.
|b online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
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|a online resource
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|a text file
|b PDF
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|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 4367
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| 505 |
0 |
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|a Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints.
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| 650 |
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0 |
|a Computer science.
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| 650 |
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|a Computer arithmetic and logic units.
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| 650 |
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|a Microprocessors.
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| 650 |
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|a Computer architecture.
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| 650 |
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|a Computer input-output equipment.
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| 650 |
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|a Logic design.
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| 650 |
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|a Computer networks .
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| 650 |
1 |
4 |
|a Theory of Computation.
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| 650 |
2 |
4 |
|a Arithmetic and Logic Structures.
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| 650 |
2 |
4 |
|a Processor Architectures.
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| 650 |
2 |
4 |
|a Input/Output and Data Communications.
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| 650 |
2 |
4 |
|a Logic Design.
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| 650 |
2 |
4 |
|a Computer Communication Networks.
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| 700 |
1 |
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|a De Bosschere, Koen.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
|
|a Kaeli, David.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
|
|a Stenström, Per.
|e editor.
|0 (orcid)0000-0002-7441-8245
|1 https://orcid.org/0000-0002-7441-8245
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
|
|a Whalley, David.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
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|a Ungerer, Theo.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 710 |
2 |
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|a SpringerLink (Online service)
|
| 773 |
0 |
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|t Springer Nature eBook
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| 776 |
0 |
8 |
|i Printed edition:
|z 9783540834571
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| 776 |
0 |
8 |
|i Printed edition:
|z 9783540693376
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| 830 |
|
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|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 4367
|
| 856 |
4 |
0 |
|u https://doi.uam.elogim.com/10.1007/978-3-540-69338-3
|z Texto Completo
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| 912 |
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|a ZDB-2-SCS
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|a ZDB-2-SXCS
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| 912 |
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|a ZDB-2-LNC
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| 950 |
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|a Computer Science (SpringerNature-11645)
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| 950 |
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|a Computer Science (R0) (SpringerNature-43710)
|
