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|a 9783540320302
|9 978-3-540-32030-2
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|a 10.1007/11560548
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|a 004.0151
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|a Correct Hardware Design and Verification Methods
|h [electronic resource] :
|b 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings /
|c edited by Dominique Borrione, Wolfgang Paul.
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| 250 |
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|a 1st ed. 2005.
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| 264 |
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|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2005.
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| 300 |
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|a XII, 414 p.
|b online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
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|a online resource
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|a text file
|b PDF
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|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 3725
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| 505 |
0 |
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|a Invited Talks -- Is Formal Verification Bound to Remain a Junior Partner of Simulation? -- Verification Challenges in Configurable Processor Design with ASIP Meister -- Tutorial -- Towards the Pervasive Verification of Automotive Systems -- Functional Approaches to Design Description -- Wired: Wire-Aware Circuit Design -- Formalization of the DE2 Language -- Game Solving Approaches -- Finding and Fixing Faults -- Verifying Quantitative Properties Using Bound Functions -- Abstraction -- How Thorough Is Thorough Enough? -- Interleaved Invariant Checking with Dynamic Abstraction -- Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units -- Algorithms and Techniques for Speeding (DD-Based) Verification 1 -- Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting -- Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation -- Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning -- Real Time and LTL Model Checking -- Real-Time Model Checking Is Really Simple -- Temporal Modalities for Concisely Capturing Timing Diagrams -- Regular Vacuity -- Algorithms and Techniques for Speeding Verification 2 -- Automatic Generation of Hints for Symbolic Traversal -- Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies -- A New SAT-Based Algorithm for Symbolic Trajectory Evaluation -- Evaluation of SAT-Based Tools -- An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment -- Model Reduction -- Exploiting Constraints in Transformation-Based Verification -- Identification and Counter Abstraction for Full Virtual Symmetry -- Verification of Memory Hierarchy Mechanisms -- On the Verification of Memory Management Mechanisms -- Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification -- Short Papers -- Symbolic Partial Order Reduction for Rule Based Transition Systems -- Verifying Timing Behavior by Abstract Interpretation of Executable Code -- Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths -- Deadlock Prevention in the Æthereal Protocol -- Acceleration of SAT-Based Iterative Property Checking -- Error Detection Using BMC in a Parallel Environment -- Formal Verification of Synchronizers -- A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems -- Improvements to the Implementation of Interpolant-Based Model Checking -- High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design -- Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic -- Resolving Quartz Overloading -- FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers -- Predictive Reachability Using a Sample-Based Approach -- Minimizing Counterexample of ACTL Property -- Data Refinement for Synchronous System Specification and Construction -- Introducing Abstractions via Rewriting -- A Case Study: Formal Verification of Processor Critical Properties.
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| 650 |
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|a Computer science.
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| 650 |
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|a Computers.
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| 650 |
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|a Software engineering.
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| 650 |
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|a Machine theory.
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| 650 |
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|a Artificial intelligence.
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| 650 |
1 |
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|a Theory of Computation.
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| 650 |
2 |
4 |
|a Computer Hardware.
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| 650 |
2 |
4 |
|a Computer Science Logic and Foundations of Programming.
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| 650 |
2 |
4 |
|a Software Engineering.
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| 650 |
2 |
4 |
|a Formal Languages and Automata Theory.
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| 650 |
2 |
4 |
|a Artificial Intelligence.
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| 700 |
1 |
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|a Borrione, Dominique.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
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|a Paul, Wolfgang.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 710 |
2 |
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|a SpringerLink (Online service)
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| 773 |
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|t Springer Nature eBook
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| 776 |
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|i Printed edition:
|z 9783540816126
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| 776 |
0 |
8 |
|i Printed edition:
|z 9783540291053
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| 830 |
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|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 3725
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| 856 |
4 |
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|u https://doi.uam.elogim.com/10.1007/11560548
|z Texto Completo
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|a ZDB-2-SCS
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|a ZDB-2-SXCS
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| 950 |
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|a Computer Science (SpringerNature-11645)
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| 950 |
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|a Computer Science (R0) (SpringerNature-43710)
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