|
|
|
|
| LEADER |
00000nam a22000005i 4500 |
| 001 |
978-3-540-31940-5 |
| 003 |
DE-He213 |
| 005 |
20220115075050.0 |
| 007 |
cr nn 008mamaa |
| 008 |
100312s2005 gw | s |||| 0|eng d |
| 020 |
|
|
|a 9783540319405
|9 978-3-540-31940-5
|
| 024 |
7 |
|
|a 10.1007/11545262
|2 doi
|
| 050 |
|
4 |
|a QA268
|
| 072 |
|
7 |
|a GPJ
|2 bicssc
|
| 072 |
|
7 |
|a URY
|2 bicssc
|
| 072 |
|
7 |
|a COM053000
|2 bisacsh
|
| 072 |
|
7 |
|a GPJ
|2 thema
|
| 072 |
|
7 |
|a URY
|2 thema
|
| 082 |
0 |
4 |
|a 005.824
|2 23
|
| 245 |
1 |
0 |
|a Cryptographic Hardware and Embedded Systems - CHES 2005
|h [electronic resource] :
|b 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings /
|c edited by Josyula R. Rao, Berk Sunar.
|
| 250 |
|
|
|a 1st ed. 2005.
|
| 264 |
|
1 |
|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2005.
|
| 300 |
|
|
|a XIV, 458 p.
|b online resource.
|
| 336 |
|
|
|a text
|b txt
|2 rdacontent
|
| 337 |
|
|
|a computer
|b c
|2 rdamedia
|
| 338 |
|
|
|a online resource
|b cr
|2 rdacarrier
|
| 347 |
|
|
|a text file
|b PDF
|2 rda
|
| 490 |
1 |
|
|a Security and Cryptology ;
|v 3659
|
| 505 |
0 |
|
|a Side Channels I -- Resistance of Randomized Projective Coordinates Against Power Analysis -- Templates as Master Keys -- A Stochastic Model for Differential Side Channel Cryptanalysis -- Arithmetic for Cryptanalysis -- A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis -- Further Hidden Markov Model Cryptanalysis -- Low Resources -- Energy-Efficient Software Implementation of Long Integer Modular Arithmetic -- Short Memory Scalar Multiplication on Koblitz Curves -- Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 ?P -- Special Purpose Hardware -- SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers -- Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization -- Design of Testable Random Bit Generators -- Hardware Attacks and Countermeasures I -- Successfully Attacking Masked AES Hardware Implementations -- Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints -- Masking at Gate Level in the Presence of Glitches -- Arithmetic for Cryptography -- Bipartite Modular Multiplication -- Fast Truncated Multiplication for Cryptographic Applications -- Using an RSA Accelerator for Modular Inversion -- Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings -- Side Channel II (EM) -- EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA -- Security Limits for Compromising Emanations -- Security Evaluation Against Electromagnetic Analysis at Design Time -- Side Channel III -- On Second-Order Differential Power Analysis -- Improved Higher-Order Side-Channel Attacks with FPGA Experiments -- Trusted Computing -- Secure Data Management in Trusted Computing -- Hardware Attacks and Countermeasures II -- Data Remanence in Flash Memory Devices -- Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment -- Hardware Attacks and Countermeasures III -- DPA Leakage Models for CMOS Logic Circuits -- The "Backend Duplication" Method -- Efficient Hardware I -- Hardware Acceleration of the Tate Pairing in Characteristic Three -- Efficient Hardware for the Tate Pairing Calculation in Characteristic Three -- Efficient Hardware II -- AES on FPGA from the Fastest to the Smallest -- A Very Compact S-Box for AES.
|
| 650 |
|
0 |
|a Cryptography.
|
| 650 |
|
0 |
|a Data encryption (Computer science).
|
| 650 |
|
0 |
|a Logic design.
|
| 650 |
|
0 |
|a Computer networks .
|
| 650 |
|
0 |
|a Computers, Special purpose.
|
| 650 |
|
0 |
|a Operating systems (Computers).
|
| 650 |
|
0 |
|a Electronic data processing-Management.
|
| 650 |
1 |
4 |
|a Cryptology.
|
| 650 |
2 |
4 |
|a Logic Design.
|
| 650 |
2 |
4 |
|a Computer Communication Networks.
|
| 650 |
2 |
4 |
|a Special Purpose and Application-Based Systems.
|
| 650 |
2 |
4 |
|a Operating Systems.
|
| 650 |
2 |
4 |
|a IT Operations.
|
| 700 |
1 |
|
|a Rao, Josyula R.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Sunar, Berk.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 710 |
2 |
|
|a SpringerLink (Online service)
|
| 773 |
0 |
|
|t Springer Nature eBook
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9783540814757
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9783540284741
|
| 830 |
|
0 |
|a Security and Cryptology ;
|v 3659
|
| 856 |
4 |
0 |
|u https://doi.uam.elogim.com/10.1007/11545262
|z Texto Completo
|
| 912 |
|
|
|a ZDB-2-SCS
|
| 912 |
|
|
|a ZDB-2-SXCS
|
| 912 |
|
|
|a ZDB-2-LNC
|
| 950 |
|
|
|a Computer Science (SpringerNature-11645)
|
| 950 |
|
|
|a Computer Science (R0) (SpringerNature-43710)
|
