Memory Controllers for Mixed-Time-Criticality Systems Architectures, Methodologies and Trade-offs /

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory cont...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Goossens, Sven (Autor), Chandrasekar, Karthik (Autor), Akesson, Benny (Autor), Goossens, Kees (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Cham : Springer International Publishing : Imprint: Springer, 2016.
Edición:1st ed. 2016.
Colección:Embedded Systems,
Temas:
Electronic circuits.
Microprocessors.
Computer architecture.
Electronics.
Electronic Circuits and Systems.
Processor Architectures.
Electronics and Microelectronics, Instrumentation.
Acceso en línea:Texto Completo

MARC

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100 1 |a Goossens, Sven.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
245 1 0 |a Memory Controllers for Mixed-Time-Criticality Systems  |h [electronic resource] :  |b Architectures, Methodologies and Trade-offs /  |c by Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens. 
250 |a 1st ed. 2016. 
264 1 |a Cham :  |b Springer International Publishing :  |b Imprint: Springer,  |c 2016. 
300 |a XXVII, 202 p. 78 illus. in color.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
490 1 |a Embedded Systems,  |x 2193-0163 
505 0 |a Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols. 
520 |a This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template. 
650 0 |a Electronic circuits. 
650 0 |a Microprocessors. 
650 0 |a Computer architecture. 
650 0 |a Electronics. 
650 1 4 |a Electronic Circuits and Systems. 
650 2 4 |a Processor Architectures. 
650 2 4 |a Electronics and Microelectronics, Instrumentation. 
700 1 |a Chandrasekar, Karthik.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
700 1 |a Akesson, Benny.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
700 1 |a Goossens, Kees.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer Nature eBook 
776 0 8 |i Printed edition:  |z 9783319320939 
776 0 8 |i Printed edition:  |z 9783319320953 
776 0 8 |i Printed edition:  |z 9783319811963 
830 0 |a Embedded Systems,  |x 2193-0163 
856 4 0 |u https://doi.uam.elogim.com/10.1007/978-3-319-32094-6  |z Texto Completo 
912 |a ZDB-2-ENG 
912 |a ZDB-2-SXE 
950 |a Engineering (SpringerNature-11647) 
950 |a Engineering (R0) (SpringerNature-43712) 

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