|
|
|
|
LEADER |
00000nam a22000005i 4500 |
001 |
978-3-319-22035-2 |
003 |
DE-He213 |
005 |
20220114155605.0 |
007 |
cr nn 008mamaa |
008 |
150827s2016 sz | s |||| 0|eng d |
020 |
|
|
|a 9783319220352
|9 978-3-319-22035-2
|
024 |
7 |
|
|a 10.1007/978-3-319-22035-2
|2 doi
|
050 |
|
4 |
|a TK7867-7867.5
|
072 |
|
7 |
|a TJFC
|2 bicssc
|
072 |
|
7 |
|a TEC008010
|2 bisacsh
|
072 |
|
7 |
|a TJFC
|2 thema
|
082 |
0 |
4 |
|a 621.3815
|2 23
|
100 |
1 |
|
|a Mohamed, Khaled Salah.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
|
245 |
1 |
0 |
|a IP Cores Design from Specifications to Production
|h [electronic resource] :
|b Modeling, Verification, Optimization, and Protection /
|c by Khaled Salah Mohamed.
|
250 |
|
|
|a 1st ed. 2016.
|
264 |
|
1 |
|a Cham :
|b Springer International Publishing :
|b Imprint: Springer,
|c 2016.
|
300 |
|
|
|a IX, 154 p. 153 illus., 115 illus. in color.
|b online resource.
|
336 |
|
|
|a text
|b txt
|2 rdacontent
|
337 |
|
|
|a computer
|b c
|2 rdamedia
|
338 |
|
|
|a online resource
|b cr
|2 rdacarrier
|
347 |
|
|
|a text file
|b PDF
|2 rda
|
490 |
1 |
|
|a Analog Circuits and Signal Processing,
|x 2197-1854
|
505 |
0 |
|
|a 1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions.
|
520 |
|
|
|a This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and system-on-chip (SoC) buses. Readers will also benefit from the author's practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain. A SoC case study is presented to compare traditional verification with the new verification methodologies. · Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; · Introduce a deep introduction for Verilog for both implementation and verification point of view. · Demonstrates how to use IP in applications such as memory controllers and SoC buses. · Describes a new verification methodology called bug localization; · Presents a novel scan-chain methodology for RTL debugging; · Enables readers to employ UVM methodology in straightforward, practical terms.
|
650 |
|
0 |
|a Electronic circuits.
|
650 |
|
0 |
|a Microprocessors.
|
650 |
|
0 |
|a Computer architecture.
|
650 |
|
0 |
|a Electronics.
|
650 |
1 |
4 |
|a Electronic Circuits and Systems.
|
650 |
2 |
4 |
|a Processor Architectures.
|
650 |
2 |
4 |
|a Electronics and Microelectronics, Instrumentation.
|
710 |
2 |
|
|a SpringerLink (Online service)
|
773 |
0 |
|
|t Springer Nature eBook
|
776 |
0 |
8 |
|i Printed edition:
|z 9783319220345
|
776 |
0 |
8 |
|i Printed edition:
|z 9783319220369
|
776 |
0 |
8 |
|i Printed edition:
|z 9783319373584
|
830 |
|
0 |
|a Analog Circuits and Signal Processing,
|x 2197-1854
|
856 |
4 |
0 |
|u https://doi.uam.elogim.com/10.1007/978-3-319-22035-2
|z Texto Completo
|
912 |
|
|
|a ZDB-2-ENG
|
912 |
|
|
|a ZDB-2-SXE
|
950 |
|
|
|a Engineering (SpringerNature-11647)
|
950 |
|
|
|a Engineering (R0) (SpringerNature-43712)
|