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A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof /
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The...
| Clasificación: | Libro Electrónico |
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| Autores principales: | , , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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| Edición: | 1st ed. 2014. |
| Colección: | Theoretical Computer Science and General Issues,
9000 |
| Temas: | |
| Acceso en línea: | Texto Completo |