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Hardware and Software: Verification and Testing 10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014, Proceedings /
This book constitutes the refereed proceedings of the 10th International Haifa Verification Conference, HVC 2014, held in Haifa, Israel, in November 2014. The 17 revised full papers and 4 short papers presented were carefully reviewed and selected from 43 submissions. The papers cover a wide range o...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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| Edición: | 1st ed. 2014. |
| Colección: | Programming and Software Engineering,
8855 |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 245 | 1 | 0 | |a Hardware and Software: Verification and Testing |h [electronic resource] : |b 10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014, Proceedings / |c edited by Eran Yahav. |
| 250 | |a 1st ed. 2014. | ||
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| 300 | |a XVI, 302 p. 78 illus. |b online resource. | ||
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| 490 | 1 | |a Programming and Software Engineering, |x 2945-9168 ; |v 8855 | |
| 505 | 0 | |a Using Coarse-Grained Abstractions to Verify Linearizability on TSO Architectures -- Enhancing Scenario Quality Using Quasi-Events -- Combined Bounded and Symbolic Model Checking for Incomplete Timed Systems -- DynaMate: Dynamically Inferring Loop Invariants for Automatic Full Functional Verification -- Generating Modulo-2 Linear Invariants for Hardware Model Checking -- Suraq - A Controller Synthesis Tool Using Uninterpreted Functions -- Synthesizing Finite-State Protocols from Scenarios and Requirements -- Automatic Error Localization for Software Using Deductive Verification -- Generating JML Specifications from Alloy Expressions -- Assume-Guarantee Abstraction Refinement Meets Hybrid Systems -- Handling TSO in Mechanized Linearizability Proofs -- Partial Quantifier Elimination -- Formal Verification of 800 Genetically Constructed Automata Programs: A Case Study -- A Framework to Synergize Partial Order Reduction with State Interpolation -- Reduction of Resolution Refutations and Interpolants via Subsumption -- Read, Write and Copy Dependencies for Symbolic Model Checking -- Efficient Combinatorial Test Generation Based on Multivalued Decision Diagrams -- Formal Verification of Secure User Mode Device Execution with DMA -- Supervisory Control of Discrete-Event Systems via IC3 -- Partial-Order Reduction for Multi-core LTL Model Checking -- A Comparative Study of Incremental Constraint Solving Approaches in Symbolic Execution. | |
| 520 | |a This book constitutes the refereed proceedings of the 10th International Haifa Verification Conference, HVC 2014, held in Haifa, Israel, in November 2014. The 17 revised full papers and 4 short papers presented were carefully reviewed and selected from 43 submissions. The papers cover a wide range of topics in the sub-fields of testing and verification applicable to software, hardware, and complex hybrid systems. | ||
| 650 | 0 | |a Software engineering. | |
| 650 | 0 | |a Computer science. | |
| 650 | 0 | |a Compilers (Computer programs). | |
| 650 | 0 | |a Artificial intelligence. | |
| 650 | 0 | |a Machine theory. | |
| 650 | 0 | |a Computer networks . | |
| 650 | 1 | 4 | |a Software Engineering. |
| 650 | 2 | 4 | |a Computer Science Logic and Foundations of Programming. |
| 650 | 2 | 4 | |a Compilers and Interpreters. |
| 650 | 2 | 4 | |a Artificial Intelligence. |
| 650 | 2 | 4 | |a Formal Languages and Automata Theory. |
| 650 | 2 | 4 | |a Computer Communication Networks. |
| 700 | 1 | |a Yahav, Eran. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
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