SVA: The Power of Assertions in SystemVerilog
This book is a comprehensive guide to assertion-based verification of hardware designs using SystemVerilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection, and formal analysis. The book provide...
Clasificación: | Libro Electrónico |
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Autores principales: | Cerny, Eduard (Autor), Dudani, Surrendra (Autor), Havlicek, John (Autor), Korchemny, Dmitry (Autor) |
Autor Corporativo: | SpringerLink (Online service) |
Formato: | Electrónico eBook |
Idioma: | Inglés |
Publicado: |
Cham :
Springer International Publishing : Imprint: Springer,
2015.
|
Edición: | 2nd ed. 2015. |
Temas: | |
Acceso en línea: | Texto Completo |
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