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Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors

This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded processors. Coverage begins with an extensive disc...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Azambuja, José Rodrigo (Autor), Kastensmidt, Fernanda (Autor), Becker, Jürgen (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Cham : Springer International Publishing : Imprint: Springer, 2014.
Edición:1st ed. 2014.
Temas:
Acceso en línea:Texto Completo

MARC

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100 1 |a Azambuja, José Rodrigo.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
245 1 0 |a Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors  |h [electronic resource] /  |c by José Rodrigo Azambuja, Fernanda Kastensmidt, Jürgen Becker. 
250 |a 1st ed. 2014. 
264 1 |a Cham :  |b Springer International Publishing :  |b Imprint: Springer,  |c 2014. 
300 |a XVIII, 94 p. 37 illus., 11 illus. in color.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
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505 0 |a Introduction -- Background -- Fault Tolerance Techniques for Processors -- Proposed Techniques to Detect Transient Faults in Processors -- Simulation Fault Injection Experimental Results -- Configuration Bitstream Fault Injection Experimental Results -- Radiation Experimental Results -- Conclusions and Future Work. 
520 |a This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded processors. Coverage begins with an extensive discussion of the current state-of-the-art in fault tolerance techniques. The authors then discuss the best trade-off between software-based and hardware-based techniques and introduce novel hybrid techniques. Proposed techniques increase existing fault detection rates up to 100%, while maintaining low performance overheads in area and application execution time. • Discusses the effects of radiation on modern integrated circuits; • Provides a comprehensive overview of state-of-the art fault tolerance techniques based on software, hardware, and hybrid techniques; • Introduces novel hybrid fault tolerance techniques for reconfigurable FPGAs and ASICs; • Performs fault injection campaigns by simulation, bitstream fault injection, and radiation experiments; • Enables readers to use techniques with lower performance degradation, area occupation, and memory usage. 
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