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High-Bandwidth Memory Interface
This book provides an overview of recent advances in memory interface design at both the architecture and circuit levels. Coverage includes signal integrity and testing, TSV interface, high-speed serial interface including equalization, ODT, pre-emphasis, wide I/O interface including crosstalk, skew...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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| Edición: | 1st ed. 2014. |
| Colección: | SpringerBriefs in Electrical and Computer Engineering,
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| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
| LEADER | 00000nam a22000005i 4500 | ||
|---|---|---|---|
| 001 | 978-3-319-02381-6 | ||
| 003 | DE-He213 | ||
| 005 | 20220120020835.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 131027s2014 sz | s |||| 0|eng d | ||
| 020 | |a 9783319023816 |9 978-3-319-02381-6 | ||
| 024 | 7 | |a 10.1007/978-3-319-02381-6 |2 doi | |
| 050 | 4 | |a TK7867-7867.5 | |
| 072 | 7 | |a TJFC |2 bicssc | |
| 072 | 7 | |a TEC008010 |2 bisacsh | |
| 072 | 7 | |a TJFC |2 thema | |
| 082 | 0 | 4 | |a 621.3815 |2 23 |
| 100 | 1 | |a Kim, Chulwoo. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a High-Bandwidth Memory Interface |h [electronic resource] / |c by Chulwoo Kim, Hyun-Woo Lee, Junyoung Song. |
| 250 | |a 1st ed. 2014. | ||
| 264 | 1 | |a Cham : |b Springer International Publishing : |b Imprint: Springer, |c 2014. | |
| 300 | |a VIII, 88 p. 91 illus., 41 illus. in color. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 490 | 1 | |a SpringerBriefs in Electrical and Computer Engineering, |x 2191-8120 | |
| 505 | 0 | |a An introduction to high-speed DRAM -- An I/O Line Configuration and Organization of DRAM -- Clock generation and distribution -- Transceiver Design -- TSV Interface for DRAM. | |
| 520 | |a This book provides an overview of recent advances in memory interface design at both the architecture and circuit levels. Coverage includes signal integrity and testing, TSV interface, high-speed serial interface including equalization, ODT, pre-emphasis, wide I/O interface including crosstalk, skew cancellation, and clock generation and distribution. Trends for further bandwidth enhancement are also covered. • Enables readers with minimal background in memory design to understand the basics of high-bandwidth memory interface design; • Presents state-of-the-art techniques for memory interface design; • Covers memory interface design at both the circuit level and system architecture level. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Electronics. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Electronics and Microelectronics, Instrumentation. |
| 700 | 1 | |a Lee, Hyun-Woo. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Song, Junyoung. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9783319023823 |
| 776 | 0 | 8 | |i Printed edition: |z 9783319023809 |
| 830 | 0 | |a SpringerBriefs in Electrical and Computer Engineering, |x 2191-8120 | |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-3-319-02381-6 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||