Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge res...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Noia, Brandon (Autor), Chakrabarty, Krishnendu (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Cham : Springer International Publishing : Imprint: Springer, 2014.
Edición:1st ed. 2014.
Temas:
Electronic circuits.
Microprocessors.
Computer architecture.
Semiconductors.
Electronic Circuits and Systems.
Processor Architectures.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Introduction
  • Wafer Stacking and 3D Memory Test
  • Built-in Self-Test for TSVs
  • Pre-Bond TSV Test Through TSV Probing
  • Pre-Bond TSV Test Through TSV Probing
  • Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths
  • Post-Bond Test Wrappers and Emerging Test Standards
  • Test-Architecture Optimization and Test Scheduling
  • Conclusions.

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