Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge res...
Clasificación: | Libro Electrónico |
---|---|
Autores principales: | Noia, Brandon (Autor), Chakrabarty, Krishnendu (Autor) |
Autor Corporativo: | SpringerLink (Online service) |
Formato: | Electrónico eBook |
Idioma: | Inglés |
Publicado: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
|
Edición: | 1st ed. 2014. |
Temas: | |
Acceso en línea: | Texto Completo |
Ejemplares similares
-
Trace-Based Post-Silicon Validation for VLSI Circuits
por: Liu, Xiao, et al.
Publicado: (2014) -
3D Stacked Chips From Emerging Processes to Heterogeneous Systems /
Publicado: (2016) -
Exploring Memory Hierarchy Design with Emerging Memory Technologies
por: Sun, Guangyu
Publicado: (2014) -
The Boundary-Scan Handbook
por: Parker, Kenneth P.
Publicado: (2016) -
Dynamic Reconfigurable Architectures and Transparent Optimization Techniques Automatic Acceleration of Software Execution /
por: Beck Fl., Antonio Carlos Schneider, et al.
Publicado: (2010)