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UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs
This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRL...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , , , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2013.
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| Edición: | 1st ed. 2013. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 100 | 1 | |a Daněk, Martin. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs |h [electronic resource] / |c by Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński. |
| 250 | |a 1st ed. 2013. | ||
| 264 | 1 | |a New York, NY : |b Springer New York : |b Imprint: Springer, |c 2013. | |
| 300 | |a XVIII, 222 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
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| 505 | 0 | |a Introduction -- The LEON3 Processor -- Microthreaded Extensions -- The Basic UTLEON3 Architecture.- UTLEON3 Programming by Example -- UTLEON3 Implementation Details -- Execution Effieciency of the Microthread Pipeline.- Hardware Families of Threads -- I/O and Interrupt Handling in the Microthread Mode -- The IU3 Pipeline -- Excerpts from the LEON3 Instruction Set -- Relevant LEON3 Registers and Address Space Identifiers.- Scheduler Example -- Used Resources -- Tutorial. | |
| 520 | |a This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs. Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; Provides VHDL sources for the described processor; Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; Includes programming by example in the micro-threaded assembly language. . | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 0 | |a Electronics. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Processor Architectures. |
| 650 | 2 | 4 | |a Electronics and Microelectronics, Instrumentation. |
| 700 | 1 | |a Kafka, Leoš. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Kohout, Lukáš. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Sýkora, Jaroslav. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Bartosiński, Roman. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
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| 776 | 0 | 8 | |i Printed edition: |z 9781461424093 |
| 776 | 0 | 8 | |i Printed edition: |z 9781461424116 |
| 776 | 0 | 8 | |i Printed edition: |z 9781489995704 |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-1-4614-2410-9 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||