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High-Performance Computing Using FPGAs
This book is concerned with the emerging field of High Performance Reconfigurable Computing (HPRC), which aims to harness the high performance and relative low power of reconfigurable hardware-in the form Field Programmable Gate Arrays (FPGAs)-in High Performance Computing (HPC) applications. It pre...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2013.
|
| Edición: | 1st ed. 2013. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 245 | 1 | 0 | |a High-Performance Computing Using FPGAs |h [electronic resource] / |c edited by Wim Vanderbauwhede, Khaled Benkrid. |
| 250 | |a 1st ed. 2013. | ||
| 264 | 1 | |a New York, NY : |b Springer New York : |b Imprint: Springer, |c 2013. | |
| 300 | |a XI, 803 p. 232 illus. |b online resource. | ||
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| 505 | 0 | |a High-Performance Hardware Acceleration of Asset Simulations -- Monte Carlo Simulation based Financial Computing on the Maxwell FPGA Parallel Machine -- Bioinformatics Applications on the FPGA-based High-Performance Computer RIVYERA -- FPGA-Accelerated Molecular Dynamics -- FPGA-based HPRC for Bioinformatics Applications -- High-Performance Computing for Neuroinformatics using FPGA -- High-Performance FPGA-Accelerated Real-time Search -- High-Performance Data Processing over N-ary Trees -- FPGA-based Systolic Computational-Memory Array for Scalable Stencil Computations -- High performance implementation of RTM seismic modeling on FPGAs: architecture, arithmetic and power issues -- High-Performance Cryptanalysis on RIVYERA and COPACOBANA Computing Systems -- FPGA-based HPRC Systems for Scientific Applications -- Accelerating the SPICE Circuit Simulator using an FPGA - A Case Study -- The Convey Hybrid-Core Architecture -- Low Cost High Performance Reconfigurable Computing -- An FPGA-based supercomputer for statistical physics: the weird case of Janus -- Accelerate Communication, not Computation! -- High-speed torus interconnect using FPGAs -- MEMSCALE: Re-architecting memory resources for clusters -- High-performance computing based on high-speed dynamic reconfiguration -- Reconfigurable arithmetic for HPC -- Acceleration of the Discrete Element Method: From RTL to C-Based Design -- Optimising Euroben Kernels on Maxwell -- Assessing Productivity of High-Level Design Methodologies for High-Performance Reconfigurable Computers -- Maximum performance computing with dataflow engines. | |
| 520 | |a This book is concerned with the emerging field of High Performance Reconfigurable Computing (HPRC), which aims to harness the high performance and relative low power of reconfigurable hardware-in the form Field Programmable Gate Arrays (FPGAs)-in High Performance Computing (HPC) applications. It presents the latest developments in this field from applications, architecture, and tools and methodologies points of view. We hope that this work will form a reference for existing researchers in the field, and entice new researchers and developers to join the HPRC community. The book includes: Thirteen application chapters which present the most important application areas tackled by high performance reconfigurable computers, namely: financial computing, bioinformatics and computational biology, data search and processing, stencil computation e.g. computational fluid dynamics and seismic modeling, cryptanalysis, astronomical N-body simulation, and circuit simulation. Seven architecture chapters which present both commercial and academic parallel FPGA architectures, low latency and high performance FPGA-based networks and memory architectures for parallel machines, and a high speed optical dynamic reconfiguration mechanism for HPRC. Five tools and methodologies chapters which address the important issue of productivity and high performance in HPRC. These include a study of precision and arithmetic issues in HPRC, comparative studies of C-based high level synthesis tools and RTL-based approaches, taxonomy of HPRC tools and a framework of their analysis, and an integrated hardware-software-application approach to HPRC. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 0 | |a Computer science-Mathematics. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Processor Architectures. |
| 650 | 2 | 4 | |a Mathematical Applications in Computer Science. |
| 700 | 1 | |a Vanderbauwhede, Wim. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Benkrid, Khaled. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
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| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||