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System-Level Validation High-Level Modeling and Directed Test Generation Techniques /
This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, i...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2013.
|
| Edición: | 1st ed. 2013. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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|---|---|---|---|
| 001 | 978-1-4614-1359-2 | ||
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| 005 | 20220114115858.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 120925s2013 xxu| s |||| 0|eng d | ||
| 020 | |a 9781461413592 |9 978-1-4614-1359-2 | ||
| 024 | 7 | |a 10.1007/978-1-4614-1359-2 |2 doi | |
| 050 | 4 | |a TK7867-7867.5 | |
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| 100 | 1 | |a Chen, Mingsong. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a System-Level Validation |h [electronic resource] : |b High-Level Modeling and Directed Test Generation Techniques / |c by Mingsong Chen, Xiaoke Qin, Heon-Mo Koo, Prabhat Mishra. |
| 250 | |a 1st ed. 2013. | ||
| 264 | 1 | |a New York, NY : |b Springer New York : |b Imprint: Springer, |c 2013. | |
| 300 | |a XXII, 250 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 505 | 0 | |a Introduction -- Modeling and Specification of SoC Designs -- Automated Generation of Directed Tests -- Functional Test Compaction.- Property Clustering and Learning Techniques -- Decision Ordering Based Learning Techniques -- Synchronized Generation of Directed Tests -- Learning-Oriented Property Decomposition Approaches -- Directed Test Generation for Multicore Architectures -- Test Generation for Cache Coherence Validation.- Reuse of System-Level Tests for Implementation Validation -- Conclusion. | |
| 520 | |a This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Electronics. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Electronics and Microelectronics, Instrumentation. |
| 650 | 2 | 4 | |a Processor Architectures. |
| 700 | 1 | |a Qin, Xiaoke. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Koo, Heon-Mo. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Mishra, Prabhat. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9781461413608 |
| 776 | 0 | 8 | |i Printed edition: |z 9781489986290 |
| 776 | 0 | 8 | |i Printed edition: |z 9781461413585 |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-1-4614-1359-2 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||