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The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits /
This book highlights the complex issues, tasks and skills that must be mastered by an IP designer, in order to design an optimized and robust digital circuit to solve a problem. The techniques and methodologies described can serve as a bridge between specifications that are known to the designer and...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2012.
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| Edición: | 1st ed. 2012. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 001 | 978-1-4614-0397-5 | ||
| 003 | DE-He213 | ||
| 005 | 20220120023016.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 111007s2012 xxu| s |||| 0|eng d | ||
| 020 | |a 9781461403975 |9 978-1-4614-0397-5 | ||
| 024 | 7 | |a 10.1007/978-1-4614-0397-5 |2 doi | |
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| 100 | 1 | |a Arora, Mohit. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 4 | |a The Art of Hardware Architecture |h [electronic resource] : |b Design Methods and Techniques for Digital Circuits / |c by Mohit Arora. |
| 250 | |a 1st ed. 2012. | ||
| 264 | 1 | |a New York, NY : |b Springer New York : |b Imprint: Springer, |c 2012. | |
| 300 | |a XV, 221 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 505 | 0 | |a The World of Metastability -- Clocks and Reset -- Handling Multiple Clocks -- Clock Dividers -- Low Power Design -- The Art of Pipelining -- Handling Endianess -- Debouncing Techniques -- Design Guidelines for EMC Performance -- References. | |
| 520 | |a This book highlights the complex issues, tasks and skills that must be mastered by an IP designer, in order to design an optimized and robust digital circuit to solve a problem. The techniques and methodologies described can serve as a bridge between specifications that are known to the designer and RTL code that is final outcome, reducing significantly the time it takes to convert initial ideas and concepts into right-first-time silicon.� Coverage focuses on real problems rather than theoretical concepts, with an emphasis on design techniques across various aspects of chip-design.�� Describes techniques to help IP designers get it right the first time, creating designs optimized in terms of power, area and performance; Focuses on practical aspects of chip design and minimizes theory; Covers chip design in a consistent way, starting with basics and gradually developing advanced concepts, such as electromagnetic compatibility (EMC) design techniques and low-power design techniques such as dynamic voltage and frequency scaling (DVFS). Mohit Arora is a Senior Systems Engineer with Freescale Semiconductor. Since joining Freescale in 2005, his responsibilities have included developing systems and architecture requirements and leading the development of VoIP-based SOCs, as well as generic microcontroller SOCs. As a systems engineer, he has been involved in product definition and writing specification, working on MCU/MPU-based products for the mid-high-end industrial and consumer market space. Prior to joining Freescale, he worked for Agilent Technologies, ST Microelectronics and DCM Technologies as a design engineer and lead, focused on printing ASICs, USB2.0 PHY, PCI-Express, Infiniband and Serial ATA protocols. He earned a Bachelor's degree in Electronics and Communication Engineering from Netaji Subhas Institute of Technology (NSIT), India in 2000, has more than 30 publications in international magazine and holds a patent on serial links. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Electronics. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Electronics and Microelectronics, Instrumentation. |
| 650 | 2 | 4 | |a Processor Architectures. |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9781489996930 |
| 776 | 0 | 8 | |i Printed edition: |z 9781461403968 |
| 776 | 0 | 8 | |i Printed edition: |z 9781461403982 |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-1-4614-0397-5 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||