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Heterogeneous Multicore Processor Technologies for Embedded Systems
To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , , , , , , , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2012.
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| Edición: | 1st ed. 2012. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 020 | |a 9781461402848 |9 978-1-4614-0284-8 | ||
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| 100 | 1 | |a Uchiyama, Kunio. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Heterogeneous Multicore Processor Technologies for Embedded Systems |h [electronic resource] / |c by Kunio Uchiyama, Fumio Arakawa, Hironori Kasahara, Tohru Nojiri, Hideyuki Noda, Yasuhiro Tawara, Akio Idehara, Kenichi Iwata, Hiroaki Shikano. |
| 250 | |a 1st ed. 2012. | ||
| 264 | 1 | |a New York, NY : |b Springer New York : |b Imprint: Springer, |c 2012. | |
| 300 | |a XII, 224 p. |b online resource. | ||
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| 505 | 0 | |a Background -- Heterogeneous Multicore Architecture -- Processor Cores -- Chip Implementations -- Software Environments -- Application Programs and Systems. | |
| 520 | |a To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Computer-aided engineering. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 | 1 | |a Arakawa, Fumio. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Kasahara, Hironori. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Nojiri, Tohru. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Noda, Hideyuki. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Tawara, Yasuhiro. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Idehara, Akio. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Iwata, Kenichi. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Shikano, Hiroaki. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
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