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Variation Tolerant On-Chip Interconnects
This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm t...
| Clasificación: | Libro Electrónico |
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| Autor principal: | |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
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New York, NY :
Springer New York : Imprint: Springer,
2012.
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| Edición: | 1st ed. 2012. |
| Colección: | Analog Circuits and Signal Processing,
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| Temas: | |
| Acceso en línea: | Texto Completo |
| Sumario: | This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance. . |
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| Descripción Física: | XII, 172 p. online resource. |
| ISBN: | 9781461401315 |
| ISSN: | 2197-1854 |