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Nanoscale Memory Repair
Yield and reliability of memories have degraded with device and voltage scaling in the nano-scale era, due to ever-increasing hard/soft errors and device parameter variations. As a result, repair techniques have been indispensable for nano-scale memories. Without these techniques, even modern MPUs/...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2011.
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| Edición: | 1st ed. 2011. |
| Colección: | Integrated Circuits and Systems,
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| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
| LEADER | 00000nam a22000005i 4500 | ||
|---|---|---|---|
| 001 | 978-1-4419-7958-2 | ||
| 003 | DE-He213 | ||
| 005 | 20220113013859.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 110110s2011 xxu| s |||| 0|eng d | ||
| 020 | |a 9781441979582 |9 978-1-4419-7958-2 | ||
| 024 | 7 | |a 10.1007/978-1-4419-7958-2 |2 doi | |
| 050 | 4 | |a TK7867-7867.5 | |
| 072 | 7 | |a TJFC |2 bicssc | |
| 072 | 7 | |a TEC008010 |2 bisacsh | |
| 072 | 7 | |a TJFC |2 thema | |
| 082 | 0 | 4 | |a 621.3815 |2 23 |
| 100 | 1 | |a Horiguchi, Masashi. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Nanoscale Memory Repair |h [electronic resource] / |c by Masashi Horiguchi, Kiyoo Itoh. |
| 250 | |a 1st ed. 2011. | ||
| 264 | 1 | |a New York, NY : |b Springer New York : |b Imprint: Springer, |c 2011. | |
| 300 | |a X, 218 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 490 | 1 | |a Integrated Circuits and Systems, |x 1558-9420 | |
| 505 | 0 | |a An Introduction to Repair Techniques: Basics of Redundancy -- Basics of Error Checking and Correction -- Comparison between Redundancy and ECC -- Repairs of Logic Circuits -- Redundancy: Models of Fault Distribution -- Yield Improvement through Redundancy -- Replacement Schemes -- Intra-Subarray Replacement -- Inter-Subarray Replacement -- Subarray Replacement -- Devices for Storing Addresses -- Testing for Redundancy -- Error Checking and Correction: Linear Algebra and Linear Codes -- Galois Field -- Error-Correcting Codes -- Coding and Decoding Circuits -- Theoretical Reduction in Soft-Error and Hard-Error Rates -- Application of ECC -- Testing for ECC -- Synergistic Effect of Redundancy and ECC: Repair of Bit Faults using Synergistic Effect -- Application of Synergistic Effect. | |
| 520 | |a Yield and reliability of memories have degraded with device and voltage scaling in the nano-scale era, due to ever-increasing hard/soft errors and device parameter variations. As a result, repair techniques have been indispensable for nano-scale memories. Without these techniques, even modern MPUs/ SoCs, in which memories have dominated the area and performance, could not have been designed successfully. This book systematically describes these yield and reliability issues in terms of mathematics and engineering, as well as an array of repair techniques, based on the authors' long careers in developing memories and low-voltage CMOS circuits. Nanoscale Memory Repair gives a detailed explanation of the various yield models and calculations, as well as various, practical logic and circuits that are critical for higher yield and reliability. Presents the first comprehensive reference to reliability and repair techniques for nano-scale memories; Covers both the mathematical foundations and engineering applications of yield and reliability in nano-scale memories; Includes a variety of practical circuits and logic, critical for higher yield and reliability, which have been proven successful during the authors' extensive experience in developing memories and low-voltage CMOS circuits. . | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Computer-aided engineering. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 | 1 | |a Itoh, Kiyoo. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9781441979575 |
| 776 | 0 | 8 | |i Printed edition: |z 9781461427940 |
| 776 | 0 | 8 | |i Printed edition: |z 9781441979599 |
| 830 | 0 | |a Integrated Circuits and Systems, |x 1558-9420 | |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-1-4419-7958-2 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||