Low Power Networks-on-Chip

Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Silvano, Cristina (Editor ), Lajolo, Marcello (Editor ), Palermo, Gianluca (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Springer US : Imprint: Springer, 2011.
Edición:1st ed. 2011.
Temas:
Electronic circuits.
Computer-aided engineering.
Electronic Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Acceso en línea:Texto Completo

MARC

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505 0 |a Network-on-Chip Power Estimation -- Timing -- synchronous/asynchronous communication -- Network-on-Chip link design -- Topology exploration -- Network-on-Chip support for CMP/MPSoCs -- Network design for 3D stacked logic and memory -- Beyond the wired Network-on-Chip. 
520 |a Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; •Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings. 
650 0 |a Electronic circuits. 
650 0 |a Computer-aided engineering. 
650 1 4 |a Electronic Circuits and Systems. 
650 2 4 |a Computer-Aided Engineering (CAD, CAE) and Design. 
700 1 |a Silvano, Cristina.  |e editor.  |0 (orcid)0000-0003-1668-0883  |1 https://orcid.org/0000-0003-1668-0883  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
700 1 |a Lajolo, Marcello.  |e editor.  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
700 1 |a Palermo, Gianluca.  |e editor.  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
710 2 |a SpringerLink (Online service) 
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776 0 8 |i Printed edition:  |z 9781441969101 
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912 |a ZDB-2-SXE 
950 |a Engineering (SpringerNature-11647) 
950 |a Engineering (R0) (SpringerNature-43712) 

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