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On and Off-Chip Crosstalk Avoidance in VLSI Design
On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus t...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2010.
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| Edición: | 1st ed. 2010. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 250 | |a 1st ed. 2010. | ||
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| 505 | 0 | |a On-Chip Crosstalk and Avoidance -- of On-Chip Crosstalk Avoidance -- Preliminaries to On-chip Crosstalk -- Memoryless Crosstalk Avoidance Codes -- CODEC Designs for Memoryless Crosstalk Avoidance Codes -- Memory-based Crosstalk Avoidance Codes -- Multi-valued Logic Crosstalk Avoidance Codes -- Summary of On-Chip Crosstalk Avoidance -- Off-Chip Crosstalk and Avoidance -- to Off-Chip Crosstalk -- Package Construction and Electrical Modeling -- Preliminaries and Terminology -- Analytical Model for Off-Chip Bus Performance -- Optimal Bus Sizing -- Bus Expansion Encoder -- Bus Stuttering Encoder -- Impedance Compensation -- Future Trends and Applications -- Summary of Off-Chip Crosstalk Avoidance. | |
| 520 | |a On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford. | ||
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| 700 | 1 | |a LaMeres, Brock J. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
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