Generating Hardware Assertion Checkers For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring /

Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the life...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Boulé, Marc (Autor), Zilic, Zeljko (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Dordrecht : Springer Netherlands : Imprint: Springer, 2008.
Edición:1st ed. 2008.
Temas:
Electronic circuits.
Computer science.
Compilers (Computer programs).
Electronic Circuits and Systems.
Theory of Computation.
Compilers and Interpreters.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Assertions and the Verification Landscape
  • Basic Techniques Behind Assertion Checkers
  • PSL and SVA Assertion Languages
  • Automata for Assertion Checkers
  • Construction of PSL Assertion Checkers
  • Enhanced Features and Uses of PSL Checkers
  • Evaluating and Verifying PSL Assertion Checkers
  • Checkers for SystemVerilog Assertions
  • Conclusions and Future Work.

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