Cargando…
Low-Power High-Speed ADCs for Nanometer CMOS Integration
Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2008.
|
| Edición: | 1st ed. 2008. |
| Colección: | Analog Circuits and Signal Processing,
|
| Temas: | |
| Acceso en línea: | Texto Completo |
Tabla de Contenidos:
- A 52 mW 10 b 210 MS/s Two-Step ADC for Digital IF Receivers in 130 nm CMOS
- A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS
- A 0.4 ps-RMS-Jitter 1-3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification
- Conclusions and Future Directions.