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Low-Power High-Speed ADCs for Nanometer CMOS Integration
Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2008.
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| Edición: | 1st ed. 2008. |
| Colección: | Analog Circuits and Signal Processing,
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| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 001 | 978-1-4020-8450-8 | ||
| 003 | DE-He213 | ||
| 005 | 20220113024509.0 | ||
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| 008 | 100301s2008 ne | s |||| 0|eng d | ||
| 020 | |a 9781402084508 |9 978-1-4020-8450-8 | ||
| 024 | 7 | |a 10.1007/978-1-4020-8450-8 |2 doi | |
| 050 | 4 | |a TK7867-7867.5 | |
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| 100 | 1 | |a Cao, Zhiheng. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Low-Power High-Speed ADCs for Nanometer CMOS Integration |h [electronic resource] / |c by Zhiheng Cao, Shouli Yan. |
| 250 | |a 1st ed. 2008. | ||
| 264 | 1 | |a Dordrecht : |b Springer Netherlands : |b Imprint: Springer, |c 2008. | |
| 300 | |a XIII, 95 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
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| 490 | 1 | |a Analog Circuits and Signal Processing, |x 2197-1854 | |
| 505 | 0 | |a A 52 mW 10 b 210 MS/s Two-Step ADC for Digital IF Receivers in 130 nm CMOS -- A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS -- A 0.4 ps-RMS-Jitter 1-3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification -- Conclusions and Future Directions. | |
| 520 | |a Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Electric power production. | |
| 650 | 0 | |a Energy policy. | |
| 650 | 0 | |a Energy and state. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Electrical Power Engineering. |
| 650 | 2 | 4 | |a Mechanical Power Engineering. |
| 650 | 2 | 4 | |a Energy Policy, Economics and Management. |
| 700 | 1 | |a Yan, Shouli. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9789048178858 |
| 776 | 0 | 8 | |i Printed edition: |z 9789048120031 |
| 776 | 0 | 8 | |i Printed edition: |z 9781402084492 |
| 830 | 0 | |a Analog Circuits and Signal Processing, |x 2197-1854 | |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-1-4020-8450-8 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||