Digital VLSI Design with Verilog A Textbook from Silicon Valley Technical Institute /

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,0...

Descripción completa

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Williams, John (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Dordrecht : Springer Netherlands : Imprint: Springer, 2008.
Edición:1st ed. 2008.
Temas:
Electronic circuits.
Compilers (Computer programs).
Electronic Circuits and Systems.
Compilers and Interpreters.
Acceso en línea:Texto Completo

MARC

LEADER 00000nam a22000005i 4500
001 978-1-4020-8446-1
003 DE-He213
005 20220119231423.0
007 cr nn 008mamaa
008 100301s2008 ne | s |||| 0|eng d
020 |a 9781402084461  |9 978-1-4020-8446-1 
024 7 |a 10.1007/978-1-4020-8446-1  |2 doi 
050 4 |a TK7867-7867.5 
072 7 |a TJFC  |2 bicssc 
072 7 |a TEC008010  |2 bisacsh 
072 7 |a TJFC  |2 thema 
082 0 4 |a 621.3815  |2 23 
100 1 |a Williams, John.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
245 1 0 |a Digital VLSI Design with Verilog  |h [electronic resource] :  |b A Textbook from Silicon Valley Technical Institute /  |c by John Williams. 
250 |a 1st ed. 2008. 
264 1 |a Dordrecht :  |b Springer Netherlands :  |b Imprint: Springer,  |c 2008. 
300 |a XXIV, 436 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
505 0 |a Week 1 Class 1 -- Week 1 Class 2 -- Week 2 Class 1 -- Week 2 Class 2 -- Week 3 Class 1 -- Week 3 Class 2 -- Week 4 Class 1 -- Week 4 Class 2 -- Week 5 Class 1 -- Week 5 Class 2 -- Week 6 Class 1 -- Week 6 Class 2 -- Week 7 Class 1 -- Week 7 Class 2 -- Week 8 Class 1 -- Week 8 Class 2 -- Week 9 Class 1 -- Week 9 Class 2 -- Week 10 Class 1 -- Week 10 Class 2 -- Week 11 Class 1 -- Week 11 Class 2 -- Week 12 Class 1 -- Week 12 Class 2. 
520 |a This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parity and ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered. 
650 0 |a Electronic circuits. 
650 0 |a Compilers (Computer programs). 
650 1 4 |a Electronic Circuits and Systems. 
650 2 4 |a Compilers and Interpreters. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer Nature eBook 
776 0 8 |i Printed edition:  |z 9789048120017 
776 0 8 |i Printed edition:  |z 9789401780490 
776 0 8 |i Printed edition:  |z 9781402084454 
856 4 0 |u https://doi.uam.elogim.com/10.1007/978-1-4020-8446-1  |z Texto Completo 
912 |a ZDB-2-ENG 
912 |a ZDB-2-SXE 
950 |a Engineering (SpringerNature-11647) 
950 |a Engineering (R0) (SpringerNature-43712) 

Ejemplares similares