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Clock Generators for SOC Processors Circuits and Architectures /
Current literature is filled with textbooks and research papers describing frequency synthesizers from a front-end wireless transceiver perspective. The emphasis has historically been on evaluating the frequency synthesizer's performance in the frequency domain, i.e. in terms of phase noise and...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2005.
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| Edición: | 1st ed. 2005. |
| Temas: | |
| Acceso en línea: | Texto Completo |
Tabla de Contenidos:
- Phase-Locked Loop Fundamentals
- Low-Voltage Analog Cmos Design
- Jitter Analysis in Phase-Locked Loops
- Low-Jitter PLL Architectures
- Digital PLL Design
- DSP Clock Generator Architectures
- Design for Testability in PLLs
- Clock Partitioning and Skew Control.