Full-Chip Nanometer Routing Techniques

As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of phys...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Ho, Tsung-Yi (Autor), Chang, Yao-Wen (Autor), Chen, Sao-Jie (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Dordrecht : Springer Netherlands : Imprint: Springer, 2007.
Edición:1st ed. 2007.
Colección:Analog Circuits and Signal Processing,
Temas:
Electronic circuits.
Computer-aided engineering.
Nanotechnology.
Electronic Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Routing Challenges for Nanometer Technology
  • Multilevel Full-Chip Routing Considering Crosstalk And Performance
  • Multilevel Full-Chip Routing Considering Antenna Effect Avoidance
  • Multilevel Full-Chip Routing For The X-Based Architecture
  • Concluding Remarks And Future Work.

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