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Co-Design for System Acceleration A Quantitative Approach /

In Co-Design for System Acceleration, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architectu...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Nedjah, Nadia (Editor ), Mourelle, Luiza (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Dordrecht : Springer Netherlands : Imprint: Springer, 2007.
Edición:1st ed. 2007.
Temas:
Acceso en línea:Texto Completo

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245 1 0 |a Co-Design for System Acceleration  |h [electronic resource] :  |b A Quantitative Approach /  |c edited by Nadia Nedjah, Luiza Mourelle. 
250 |a 1st ed. 2007. 
264 1 |a Dordrecht :  |b Springer Netherlands :  |b Imprint: Springer,  |c 2007. 
300 |a XIX, 229 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
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505 0 |a The Co-design Methodology -- The Co-design System -- VHDL Model of the Co-design System -- Shared Memory Configuration -- Dual-port Memory Configuration -- Cache Memory Configuration -- Advanced Topics and Further Research. 
520 |a In Co-Design for System Acceleration, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism. The content of Co-Design for System Acceleration is divided into eight chapters. We present co-design as a methodology for the integrated design of systems implemented using both hardware and software components. This includes high-level synthesis and the new technologies available for its implementation. The physical co-design system is then presented. The development route adopted is discussed and the target architecture described. The relation between the execution times and the interface mechanisms is analyzed. In order to investigate the performance of the co-design system for different characteristics of the application and of the architecture, we developed a VHDL model of our co-design system. The timing characteristics of the system are introduced, that is times for parameter passing and bus arbitration for each interface mechanism, together with their handshake completion times. The relation between the coprocessor memory accesses and the interface mechanisms is then studied. Several memory configurations are presented and studied: single-port memory, dual-port memory and cache memory. We also introduce some new trends in co-design and system acceleration. 
650 0 |a Electronic circuits. 
650 0 |a Computers. 
650 0 |a Computer engineering. 
650 0 |a Computer networks . 
650 0 |a Computer storage devices. 
650 0 |a Memory management (Computer science). 
650 0 |a Microprocessors. 
650 0 |a Computer architecture. 
650 1 4 |a Electronic Circuits and Systems. 
650 2 4 |a Computer Hardware. 
650 2 4 |a Computer Engineering and Networks. 
650 2 4 |a Computer Memory Structure. 
650 2 4 |a Processor Architectures. 
700 1 |a Nedjah, Nadia.  |e editor.  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
700 1 |a Mourelle, Luiza.  |e editor.  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer Nature eBook 
776 0 8 |i Printed edition:  |z 9789048173884 
776 0 8 |i Printed edition:  |z 9789048111466 
776 0 8 |i Printed edition:  |z 9781402055454 
856 4 0 |u https://doi.uam.elogim.com/10.1007/978-1-4020-5546-1  |z Texto Completo 
912 |a ZDB-2-ENG 
912 |a ZDB-2-SXE 
950 |a Engineering (SpringerNature-11647) 
950 |a Engineering (R0) (SpringerNature-43712)