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Fast, Efficient and Predictable Memory Accesses Optimization Algorithms for Memory Architecture Aware Compilation /

Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the level...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Wehmeyer, Lars (Autor), Marwedel, Peter (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Dordrecht : Springer Netherlands : Imprint: Springer, 2006.
Edición:1st ed. 2006.
Temas:
Acceso en línea:Texto Completo

MARC

LEADER 00000nam a22000005i 4500
001 978-1-4020-4822-7
003 DE-He213
005 20220118141026.0
007 cr nn 008mamaa
008 100301s2006 ne | s |||| 0|eng d
020 |a 9781402048227  |9 978-1-4020-4822-7 
024 7 |a 10.1007/1-4020-4822-X  |2 doi 
050 4 |a TK7867-7867.5 
072 7 |a TJFC  |2 bicssc 
072 7 |a TEC008010  |2 bisacsh 
072 7 |a TJFC  |2 thema 
082 0 4 |a 621.3815  |2 23 
100 1 |a Wehmeyer, Lars.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
245 1 0 |a Fast, Efficient and Predictable Memory Accesses  |h [electronic resource] :  |b Optimization Algorithms for Memory Architecture Aware Compilation /  |c by Lars Wehmeyer, Peter Marwedel. 
250 |a 1st ed. 2006. 
264 1 |a Dordrecht :  |b Springer Netherlands :  |b Imprint: Springer,  |c 2006. 
300 |a XII, 258 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
505 0 |a Abstract -- Models and Tools -- Scratchpad Memory Optimizations -- Main Memory Optimizations -- Register File Optimization -- Summary -- Future Work. 
520 |a Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy. 
650 0 |a Electronic circuits. 
650 0 |a Computer systems. 
650 0 |a Operating systems (Computers). 
650 0 |a Microprocessors. 
650 0 |a Computer architecture. 
650 0 |a Optical materials. 
650 0 |a Electronics. 
650 1 4 |a Electronic Circuits and Systems. 
650 2 4 |a Computer System Implementation. 
650 2 4 |a Operating Systems. 
650 2 4 |a Processor Architectures. 
650 2 4 |a Optical Materials. 
650 2 4 |a Electronics and Microelectronics, Instrumentation. 
700 1 |a Marwedel, Peter.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer Nature eBook 
776 0 8 |i Printed edition:  |z 9789048172009 
776 0 8 |i Printed edition:  |z 9789048108787 
776 0 8 |i Printed edition:  |z 9781402048210 
856 4 0 |u https://doi.uam.elogim.com/10.1007/1-4020-4822-X  |z Texto Completo 
912 |a ZDB-2-ENG 
912 |a ZDB-2-SXE 
950 |a Engineering (SpringerNature-11647) 
950 |a Engineering (R0) (SpringerNature-43712)