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VLSI-SoC: Advanced Topics on Systems on a Chip A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007), October 15-17, 2007, Atlanta, USA /

International Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Reis, Ricardo (Editor ), Mooney, Vincent (Editor ), Hasler, Paul (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Springer US : Imprint: Springer, 2009.
Edición:1st ed. 2009.
Colección:IFIP Advances in Information and Communication Technology, 291
Temas:
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.
  • Use of Gray Decoding for Implementation of Symmetric Functions
  • A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier
  • Compression-based SoC Test Infrastructures
  • Parametric Structure-Preserving Model Order Reduction
  • ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching
  • QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques
  • Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis
  • Statistical and Numerical Approach for a Computer efficient circuit yield analysis
  • SWORD: A SAT like Prover Using Word Level Information
  • A new analytical approach of the impact of jitter on continuous time delta sigma converters.
  • An adaptive genetic algorithm for dynamically reconfigurable modules allocation
  • The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm
  • System and Procesor Design Effort Estimation
  • Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors
  • First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model.