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Wafer Level 3-D ICs Process Technology
Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for impro...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2008.
|
| Edición: | 1st ed. 2008. |
| Colección: | Integrated Circuits and Systems,
|
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 245 | 1 | 0 | |a Wafer Level 3-D ICs Process Technology |h [electronic resource] / |c edited by Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif. |
| 250 | |a 1st ed. 2008. | ||
| 264 | 1 | |a New York, NY : |b Springer US : |b Imprint: Springer, |c 2008. | |
| 300 | |a XII, 410 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
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| 490 | 1 | |a Integrated Circuits and Systems, |x 1558-9420 | |
| 505 | 0 | |a Overview of Wafer-Level 3D ICs -- Monolithic 3D Integrated Circuits -- Stacked CMOS Technologies -- Wafer-Bonding Technologies and Strategies for 3D ICs -- Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies -- Cu Wafer Bonding for 3D IC Applications -- Cu/Sn Solid#x2013;Liquid Interdiffusion Bonding -- An SOI-Based 3D Circuit Integration Technology -- 3D Fabrication Options for High-Performance CMOS Technology -- 3D Integration Based upon Dielectric Adhesive Bonding -- Direct Hybrid Bonding -- 3D Memory -- Circuit Architectures for 3D Integration -- Thermal Challenges of 3D ICs -- Status and Outlook. | |
| 520 | |a Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration. Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration. | ||
| 650 | 0 | |a Electronics. | |
| 650 | 0 | |a Optical materials. | |
| 650 | 0 | |a Surfaces (Technology). | |
| 650 | 0 | |a Thin films. | |
| 650 | 0 | |a Engineering. | |
| 650 | 1 | 4 | |a Electronics and Microelectronics, Instrumentation. |
| 650 | 2 | 4 | |a Optical Materials. |
| 650 | 2 | 4 | |a Surfaces, Interfaces and Thin Film. |
| 650 | 2 | 4 | |a Technology and Engineering. |
| 700 | 1 | |a Tan, Chuan Seng. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Gutmann, Ronald J. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Reif, L. Rafael. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
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