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Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) r...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2008.
|
| Edición: | 1st ed. 2008. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 001 | 978-0-387-76474-0 | ||
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| 005 | 20220118010000.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 100301s2008 xxu| s |||| 0|eng d | ||
| 020 | |a 9780387764740 |9 978-0-387-76474-0 | ||
| 024 | 7 | |a 10.1007/978-0-387-76474-0 |2 doi | |
| 050 | 4 | |a TK7867-7867.5 | |
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| 072 | 7 | |a TJFC |2 thema | |
| 082 | 0 | 4 | |a 621.3815 |2 23 |
| 100 | 1 | |a Mohanty, Saraju P. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Low-Power High-Level Synthesis for Nanoscale CMOS Circuits |h [electronic resource] / |c by Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyardarsan Patra. |
| 250 | |a 1st ed. 2008. | ||
| 264 | 1 | |a New York, NY : |b Springer US : |b Imprint: Springer, |c 2008. | |
| 300 | |a XXXII, 302 p. 20 illus. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 505 | 0 | |a High-Level Synthesis Fundamentals -- Power Modeling and Estimation at Transistor and Logic Gate Levels -- Architectural Power Modeling and Estimation -- Power Reduction Fundamentals -- Energy or Average Power Reduction -- Peak Power Reduction -- Transient Power Reduction -- Leakage Power Reduction -- Conclusions and Future Direction. | |
| 520 | |a Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation. The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including: • Power Reduction Fundamentals • Energy or Average Power Reduction • Peak Power Reduction • Transient Power Reduction • Leakage Power Reduction Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Electronics. | |
| 650 | 0 | |a Computer-aided engineering. | |
| 650 | 0 | |a Computers. | |
| 650 | 0 | |a Electrical engineering. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Electronics and Microelectronics, Instrumentation. |
| 650 | 2 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design. |
| 650 | 2 | 4 | |a Computer Hardware. |
| 650 | 2 | 4 | |a Electrical and Electronic Engineering. |
| 700 | 1 | |a Ranganathan, Nagarajan. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Kougianos, Elias. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Patra, Priyardarsan. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9780387523231 |
| 776 | 0 | 8 | |i Printed edition: |z 9781441945549 |
| 776 | 0 | 8 | |i Printed edition: |z 9780387764733 |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-0-387-76474-0 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||