VLSI-SoC: Research Trends in VLSI and Systems on Chip Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France /
International Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications...
Clasificación: | Libro Electrónico |
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Autor Corporativo: | |
Otros Autores: | , , |
Formato: | Electrónico eBook |
Idioma: | Inglés |
Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2008.
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Edición: | 1st ed. 2008. |
Colección: | IFIP Advances in Information and Communication Technology,
249 |
Temas: | |
Acceso en línea: | Texto Completo |
Tabla de Contenidos:
- Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits
- Oversampled Time Estimation Techniques for Precision Photonic Detectors
- Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices
- Electronic Detection of DNA Adsorption and Hybridization
- Probabilistic amp; Statistical Design-the Wave of the Future
- A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs
- Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design
- Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design
- Soft Error Resilient System Design through Error Correction
- Library Compatible Variational Delay Computation
- A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures
- Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots
- Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation
- Logic Synthesis of EXOR Projected Sum of Products
- A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits
- CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization
- Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation
- Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies
- Designing Routing and Message-Dependent Deadlock Free Networks on Chips
- Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model
- Human++: Emerging Technology for Body Area Networks.