VLSI-SoC: From Systems to Silicon IFIP TC10/ WG 10.5 Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2005), October 17-19, 2005, Perth, Australia /

International Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Reis, Ricardo (Editor ), Osseiran, Adam (Editor ), Pfleiderer, Hans-Joerg (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Springer US : Imprint: Springer, 2007.
Edición:1st ed. 2007.
Colección:IFIP Advances in Information and Communication Technology, 240
Temas:
Electronic circuits.
Electronic Circuits and Systems.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Molecular Electronics - Devices and Circuits Technology
  • Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals
  • A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures
  • Defragmentation Algorithms for Partially Reconfigurable Hardware
  • Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
  • 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System
  • Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms
  • A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis
  • Issues in Model Reduction of Power Grids
  • A Traffic Injection Methodology with Support for System-Level Synchronization
  • Pareto Points in SRAM Design Using the Sleepy Stack Approach
  • Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs
  • Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping
  • A Novel MicroPhotonic Structure for Optical Header Recognition
  • Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
  • On-chip Pseudorandom Testing for Linear and Nonlinear MEMS
  • Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles
  • On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction
  • Exact BDD Minimization for Path-Related Objective Functions
  • Current Mask Generation: an Analog Circuit to Thwart DPA Attacks
  • A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.

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