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Modern Circuit Placement Best Practices and Results /
Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the signi...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2007.
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| Edición: | 1st ed. 2007. |
| Colección: | Integrated Circuits and Systems,
|
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 245 | 1 | 0 | |a Modern Circuit Placement |h [electronic resource] : |b Best Practices and Results / |c edited by Gi-Joon Nam, Jingsheng Jason Cong. |
| 250 | |a 1st ed. 2007. | ||
| 264 | 1 | |a New York, NY : |b Springer US : |b Imprint: Springer, |c 2007. | |
| 300 | |a XX, 324 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
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| 490 | 1 | |a Integrated Circuits and Systems, |x 1558-9420 | |
| 505 | 0 | |a Benchmarks -- ISPD 2005/2006 Placement Benchmarks -- Locality and Utilization in Placement Suboptimality -- Flat Placement Techniques -- DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective -- Kraftwerk: A Fast and Robust Quadratic Placer Using an Exact Linear Net Model -- Top-Down Partitioning-Based Techniques -- Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability -- Congestion Minimization in Modern Placement Circuits -- Multilevel Placement Techniques -- APlace: A High Quality, Large-Scale Analytical Placer -- FastPlace: An Efficient Multilevel Force-Directed Placement Algorithm -- mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement -- mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control -- NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs -- Conclusion and Challenges. | |
| 520 | |a Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the significance of interconnect optimization becomes much more important and physical design, particularly the placement process, is essential to interconnect optimization. This book has four unique characteristics. First, it focuses on the most recent highly scalable placement techniques used for multi-million gate circuit designs, with consideration of many practical aspects of modern circuit placement, such as density and routability control, mixed-size placement support, and area I/O support. Second the book addresses dominant techniques being used in the field. This book includes all the academic placement tools that competed at the International Symposium on Physical Design (ISPD) placement contest in 2005 and 2006. Although these tools are developed by academia, many core techniques in these tools are being used extensively in industry and represent today's advanced placement techniques. Third, the book provides quantitative comparison among the various techniques on common benchmark circuits derived from real-life industrial designs. The book includes significant amounts of analysis on each technique, such as trade-offs between quality-of-results (QoR) and runtime. Finally, analysis of the optimality of the placement techniques is included. This is done by utilizing placement benchmarks with known optimal solutions, yet with characteristics similar to real industrial designs. Modern Circuit Placement: Best Practices and Results is a valuable tool and a must-read for graduate students, researchers and CAD tool developers in the VLSI physical synthesis and physical design fields. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Electrical engineering. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Electrical and Electronic Engineering. |
| 700 | 1 | |a Nam, Gi-Joon. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Cong, Jingsheng Jason. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
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| 830 | 0 | |a Integrated Circuits and Systems, |x 1558-9420 | |
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