Routing Congestion in VLSI Circuits Estimation and Optimization /

With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Saxena, Prashant (Autor), Shelar, Rupesh S. (Autor), Sapatnekar, Sachin (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Springer US : Imprint: Springer, 2007.
Edición:1st ed. 2007.
Colección:Integrated Circuits and Systems,
Temas:
Electronic circuits.
Computer-aided engineering.
Telecommunication.
Electronic Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Communications Engineering, Networks.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • The Origins of Congestion
  • An Introduction to Routing Congestion
  • The Estimation of Congestion
  • Placement-level Metrics for Routing Congestion
  • Synthesis-level Metrics for Routing Congestion
  • The Optimization of Congestion
  • Congestion Optimization During Interconnect Synthesis and Routing
  • Congestion Optimization During Placement
  • Congestion Optimization During Technology Mapping and Logic Synthesis
  • Congestion Implications of High Level Design.

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