Fault-Tolerance Techniques for SRAM-Based FPGAs

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technol...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Kastensmidt, Fernanda Lima (Autor), Reis, Ricardo (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Springer US : Imprint: Springer, 2006.
Edición:1st ed. 2006.
Colección:Frontiers in Electronic Testing ; 32
Temas:
Electrical engineering.
Optical materials.
Electronics.
Engineering design.
Computers.
Logic design.
Electrical and Electronic Engineering.
Optical Materials.
Electronics and Microelectronics, Instrumentation.
Engineering Design.
Hardware Performance and Reliability.
Logic Design.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Radiation Effects in Integrated Circuits
  • Single Event Upset (SEU) Mitigation Techniques
  • Architectural SEU Mitigation Techniques
  • High-Level SEU Mitigation Techniques
  • Triple Modular Redundancy (TMR) Robustness
  • Designing and Testing a TMR Micro-Controller
  • Reducing TMR Overheads: Part I
  • Reducing TMR Overheads: Part II
  • Final Remarks.

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