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Scalable Hardware Verification with Symbolic Simulation
Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner working...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2006.
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| Edición: | 1st ed. 2006. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
| LEADER | 00000nam a22000005i 4500 | ||
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| 001 | 978-0-387-29906-8 | ||
| 003 | DE-He213 | ||
| 005 | 20220112143310.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 100301s2006 xxu| s |||| 0|eng d | ||
| 020 | |a 9780387299068 |9 978-0-387-29906-8 | ||
| 024 | 7 | |a 10.1007/0-387-29906-8 |2 doi | |
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| 100 | 1 | |a Bertacco, Valeria. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Scalable Hardware Verification with Symbolic Simulation |h [electronic resource] / |c by Valeria Bertacco. |
| 250 | |a 1st ed. 2006. | ||
| 264 | 1 | |a New York, NY : |b Springer US : |b Imprint: Springer, |c 2006. | |
| 300 | |a XX, 180 p. 40 illus. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 505 | 0 | |a Design and Verification of Digital Systems -- Symbolic Simulation -- Compacting Intermediate States -- Approximate Simulation -- Exact Parametrizations -- Conclusion. | |
| 520 | |a Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions. In structuring this book, the author's hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research. Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Computer-aided engineering. | |
| 650 | 0 | |a Computers. | |
| 650 | 0 | |a Electrical engineering. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design. |
| 650 | 2 | 4 | |a Computer Hardware. |
| 650 | 2 | 4 | |a Electrical and Electronic Engineering. |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9781441937391 |
| 776 | 0 | 8 | |i Printed edition: |z 9780387505053 |
| 776 | 0 | 8 | |i Printed edition: |z 9780387244112 |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/0-387-29906-8 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||