Leakage in Nanometer CMOS Technologies

Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumptio...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Narendra, Siva G. (Editor ), Chandrakasan, Anantha P. (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Springer US : Imprint: Springer, 2006.
Edición:1st ed. 2006.
Colección:Integrated Circuits and Systems,
Temas:
Electronic circuits.
Computer-aided engineering.
Electronics.
Computers.
Electrical engineering.
Nanotechnology.
Electronic Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electronics and Microelectronics, Instrumentation.
Computer Hardware.
Electrical and Electronic Engineering.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Taxonomy of Leakage: Sources, Impact, and Solutions
  • Leakage Dependence on Input Vector
  • Power Gating and Dynamic Voltage Scaling
  • Methodologies for Power Gating
  • Body Biasing
  • Process Variation and Adaptive Design
  • Memory Leakage Reduction
  • Active Leakage Reduction and Multi-Performance Devices
  • Impact of Leakage Power and Variation on Testing
  • Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors
  • Case Study: Leakage Reduction in the Intel Xscale Microprocessor
  • Transistor Design to Reduce Leakage.

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