Cargando…
Guide to RISC Processors for Programmers and Engineers /
Recently, there has been a trend toward processor design based on the RISC (Reduced Instruction Set Computer) model: Example RISC processors are the MIPS, SPARC, PowerPC, ARM, and even Intel's 64-bit processor Itanium. This guidebook provides an accessible and all-encompassing compendium on RIS...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2005.
|
| Edición: | 1st ed. 2005. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
| LEADER | 00000nam a22000005i 4500 | ||
|---|---|---|---|
| 001 | 978-0-387-27446-1 | ||
| 003 | DE-He213 | ||
| 005 | 20220115200104.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 100301s2005 xxu| s |||| 0|eng d | ||
| 020 | |a 9780387274461 |9 978-0-387-27446-1 | ||
| 024 | 7 | |a 10.1007/b139084 |2 doi | |
| 050 | 4 | |a TK7895.M5 | |
| 050 | 4 | |a QA76.9.A73 | |
| 072 | 7 | |a UYF |2 bicssc | |
| 072 | 7 | |a COM011000 |2 bisacsh | |
| 072 | 7 | |a UYF |2 thema | |
| 082 | 0 | 4 | |a 004.22 |2 23 |
| 100 | 1 | |a Dandamudi, Sivarama P. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Guide to RISC Processors |h [electronic resource] : |b for Programmers and Engineers / |c by Sivarama P. Dandamudi. |
| 250 | |a 1st ed. 2005. | ||
| 264 | 1 | |a New York, NY : |b Springer New York : |b Imprint: Springer, |c 2005. | |
| 300 | |a XVI, 388 p. 80 illus. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 505 | 0 | |a Overview -- Processor Design Issues -- RISC Principles -- Architectures -- MIPS Architecture -- SPARC Architecture -- PowerPC Architecture -- Itanium Architecture -- ARM Architecture -- MIPS Assembly Language -- SPIM Simulator and Debugger -- Assembly Language Overview -- Procedures and the Stack -- Addressing Modes -- Arithmetic Instructions -- Conditional Execution -- Logical and Shift Operations -- Recursion -- Floating-Point Operations. | |
| 520 | |a Recently, there has been a trend toward processor design based on the RISC (Reduced Instruction Set Computer) model: Example RISC processors are the MIPS, SPARC, PowerPC, ARM, and even Intel's 64-bit processor Itanium. This guidebook provides an accessible and all-encompassing compendium on RISC processors, introducing five RISC processors: MIPS, SPARC, PowerPC, ARM, and Itanium. Initial chapters explain the differences between the CISC and RISC designs and clearly discuss the core RISC design principles. The text then integrates instruction on MIPS assembly language programming, thereby enabling readers to concretely grasp concepts and principles introduced earlier. Readers need only have a basic knowledge of any structured, high-level language to obtain the full benefits here. Features: *Includes MIPS simulator (SPIM) download instructions, so that readers can get hands-on assembly language programming experience *Presents material in a manner suitable for flexible self-study • Assembly language programs permit reader executables using the SPIM simulator • Integrates core concepts to processor designs and their implementations • Supplies extensive and complete programming examples and figures • Contains chapter-by-chapter overviews and summaries * Provides source code for the MIPS language at the book's website Guide to RISC Processors provides a uniquely comprehensive introduction and guide to RISC-related concepts, principles, design philosophy, and actual programming, as well as the all the popular modern RISC processors and their assembly language. Professionals, programmers, and students seeking an authoritative and practical overview of RISC processors and assembly language programming will find the guide an essential resource. Sivarama P. Dandamudi is a professor of computer science at Carleton University in Ottawa, Ontario, Canada, as well as associate editor responsible for computer architecture at the International Journal of Computers and Their Applications. He has more than two decades of experience teaching about computer systems and organization. Key Topics * Processor design issues * Evolution of CISC and RISC processors * MIPS, SPARC, PowerPC, Itanium, and ARM architectures * MIPS assembly language * SPIM simulator and debugger * Conditional execution * Floating-point and logical and shift operations * Number systems Computer Architecture/Programming Beginning/Intermediate Level. | ||
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 0 | |a Microprogramming . | |
| 650 | 0 | |a Software engineering. | |
| 650 | 0 | |a Computer engineering. | |
| 650 | 0 | |a Computer networks . | |
| 650 | 0 | |a Computer programming. | |
| 650 | 1 | 4 | |a Processor Architectures. |
| 650 | 2 | 4 | |a Control Structures and Microprogramming. |
| 650 | 2 | 4 | |a Software Engineering. |
| 650 | 2 | 4 | |a Computer Engineering and Networks. |
| 650 | 2 | 4 | |a Programming Techniques. |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9780387501093 |
| 776 | 0 | 8 | |i Printed edition: |z 9781441919359 |
| 776 | 0 | 8 | |i Printed edition: |z 9780387210179 |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/b139084 |z Texto Completo |
| 912 | |a ZDB-2-SCS | ||
| 912 | |a ZDB-2-SXCS | ||
| 950 | |a Computer Science (SpringerNature-11645) | ||
| 950 | |a Computer Science (R0) (SpringerNature-43710) | ||