Advanced BDD Optimization

VLSI CADhas greatly bene?ted from the use of reduced ordered Binary Decision Diagrams (BDDs) and the clausal representation as a problem of Boolean Satis?ability (SAT), e.g. in logic synthesis, ver- cation or design-for-testability. In recent practical applications, BDDs are optimized with respect t...

Descripción completa

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Ebendt, Rudiger (Autor), Fey, Görschwin (Autor), Drechsler, Rolf (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Springer US : Imprint: Springer, 2005.
Edición:1st ed. 2005.
Temas:
Electronic circuits.
Probabilities.
Mechanical engineering.
Electrical engineering.
Engineering design.
Electronics.
Electronic Circuits and Systems.
Probability Theory.
Mechanical Engineering.
Electrical and Electronic Engineering.
Engineering Design.
Electronics and Microelectronics, Instrumentation.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Preface. 1. Introduction. 2. Preliminaries. 2.1. Notation. 2.2. Boolean Functions. 2.3. Decomposition of Boolean Functions. 2.4. Reduced Ordered Binary Decision Diagrams
  • 3. Exact node Minimization. 3.1. Branch and Bound Algorithm. 3.2. A*-Based Optimization. 3.3. Summary
  • 4. Heuristic node Minimization. 4.1. Efficient Dynamic Minimization. 4.2. Improved Lower Bounds for Dynamic Reordering. 4.3. Efficient Forms of Improved Lower Bounds. 4.4. Combination of Improved Lower Bounds with Classical Bounds. 4.5. Experimental Results. 4.6. Summary
  • 5. Path Minimization. 5.1. Minimization of Number of Paths. 5.2. Minimization of Expected Path Length. 5.3. Minimization of Average Path Length. 5.4. Summary
  • 6. Relation between SAT and BDDS. 6.1. Davis-Putnam Procedure. 6.2. On the Relation between DP Procedure and BDDs. 6.3. Dynamic Variable Ordering Strategy for DP Procedure. 6.4. Experimental Results. 6.5. Summary
  • 7. Final Remarks. References. Index.

Ejemplares similares