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Advanced BDD Optimization
VLSI CADhas greatly bene?ted from the use of reduced ordered Binary Decision Diagrams (BDDs) and the clausal representation as a problem of Boolean Satis?ability (SAT), e.g. in logic synthesis, ver- cation or design-for-testability. In recent practical applications, BDDs are optimized with respect t...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2005.
|
| Edición: | 1st ed. 2005. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
| LEADER | 00000nam a22000005i 4500 | ||
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| 001 | 978-0-387-25454-8 | ||
| 003 | DE-He213 | ||
| 005 | 20220126113050.0 | ||
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| 008 | 100301s2005 xxu| s |||| 0|eng d | ||
| 020 | |a 9780387254548 |9 978-0-387-25454-8 | ||
| 024 | 7 | |a 10.1007/b107399 |2 doi | |
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| 100 | 1 | |a Ebendt, Rudiger. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Advanced BDD Optimization |h [electronic resource] / |c by Rudiger Ebendt, Görschwin Fey, Rolf Drechsler. |
| 250 | |a 1st ed. 2005. | ||
| 264 | 1 | |a New York, NY : |b Springer US : |b Imprint: Springer, |c 2005. | |
| 300 | |a X, 222 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
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| 505 | 0 | |a Preface. 1. Introduction. 2. Preliminaries. 2.1. Notation. 2.2. Boolean Functions. 2.3. Decomposition of Boolean Functions. 2.4. Reduced Ordered Binary Decision Diagrams -- 3. Exact node Minimization. 3.1. Branch and Bound Algorithm. 3.2. A*-Based Optimization. 3.3. Summary -- 4. Heuristic node Minimization. 4.1. Efficient Dynamic Minimization. 4.2. Improved Lower Bounds for Dynamic Reordering. 4.3. Efficient Forms of Improved Lower Bounds. 4.4. Combination of Improved Lower Bounds with Classical Bounds. 4.5. Experimental Results. 4.6. Summary -- 5. Path Minimization. 5.1. Minimization of Number of Paths. 5.2. Minimization of Expected Path Length. 5.3. Minimization of Average Path Length. 5.4. Summary -- 6. Relation between SAT and BDDS. 6.1. Davis-Putnam Procedure. 6.2. On the Relation between DP Procedure and BDDs. 6.3. Dynamic Variable Ordering Strategy for DP Procedure. 6.4. Experimental Results. 6.5. Summary -- 7. Final Remarks. References. Index. | |
| 520 | |a VLSI CADhas greatly bene?ted from the use of reduced ordered Binary Decision Diagrams (BDDs) and the clausal representation as a problem of Boolean Satis?ability (SAT), e.g. in logic synthesis, ver- cation or design-for-testability. In recent practical applications, BDDs are optimized with respect to new objective functions for design space exploration. The latest trends show a growing number of proposals to fuse the concepts of BDD and SAT. This book gives a modern presentation of the established as well as of recent concepts. Latest results in BDD optimization are given, c- ering di?erent aspects of paths in BDDs and the use of e?cient lower bounds during optimization. The presented algorithms include Branch ? and Bound and the generic A -algorithm as e?cient techniques to - plore large search spaces. ? The A -algorithm originates from Arti?cial Intelligence (AI), and the EDA community has been unaware of this concept for a long time. Re- ? cently, the A -algorithm has been introduced as a new paradigm to explore design spaces in VLSI CAD. Besides AI search techniques, the book also discusses the relation to another ?eld of activity bordered to VLSI CAD and BDD optimization: the clausal representation as a SAT problem. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Probabilities. | |
| 650 | 0 | |a Mechanical engineering. | |
| 650 | 0 | |a Electrical engineering. | |
| 650 | 0 | |a Engineering design. | |
| 650 | 0 | |a Electronics. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Probability Theory. |
| 650 | 2 | 4 | |a Mechanical Engineering. |
| 650 | 2 | 4 | |a Electrical and Electronic Engineering. |
| 650 | 2 | 4 | |a Engineering Design. |
| 650 | 2 | 4 | |a Electronics and Microelectronics, Instrumentation. |
| 700 | 1 | |a Fey, Görschwin. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Drechsler, Rolf. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
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